Maybe you could also point us to some papers! What's the advantage to higher powered EUV light sources? If you can cause the photomask film to react with lower power why go higher? Also, if a particle falls onto a pellicle, how do the chip makers remove the particle? Why does the method not work for the bare masks?
OK, I'm not a semiconductor engineer, but I play one on TV. Here's my take: 1. High-powered EUV sources mean shorter exposure times, which means that you process more wafers per hour and make more money. 2. Same answer. 3. Probably initially with a clean gas spray, if that doesn't work then perhaps a clean water or solvent wash. All of which takes time and labor and has a chance of doing more damage. Note that time and labor reduces the number of wafers you can process per hour, and thus how much money you can make. 4. The Pellicle likely has a much tougher, smoother surface. The mask is likely much more easily damaged as a result.
The problem is that you could destroy many, many wafers before you noted that there was a particle. The easiest way to detect a fault is when the wafer is completely processed (all 25-50 layers exposed, developed, etched, etc) and you can test it - but that could be two to three weeks after you started processing the wafer. In the meantime, you might have hundreds or thousands of wafers that are in various stages of processing, and all of them might have the fault. The harder way to detect a fault is to try to image the wafer after each step, and see if you can detect the fault - but that would likely be very difficult and time-consuming considering that features sizes are on the order of 10 nm. What color of light would you need to resolve such a feature? An even harder way would likely be to try to image the mask and see if you can detect the fault. Imaging anything is going to take time, which will reduce the number of wafers you can process an hour, which is going to reduce the amount of money you make.
Regarding 3, Pellicles simply do not need to be cleaned as soon as a particle falls on them as said particle is out-of-focus with the mask/mirrors/light source. Depending on its specific structural characteristics an EUV pellicle could be impossible to clean so a better approach it's to just replace it with a new one.
There are inspection tools that can detect defects in the photoresist as soon as the wafer is out of the track. If a defect is detected the photoresist is just stripped and the wafer is exposed again (after correcting the cause of the defect if using the same scanner).
Modern semiconductor manufacturing would be impossible if they had to wait for a wafer to be completely processed before testing it.
A lot of work has gone into improving the absorption of the EUV by the resist on the target, the current best are tin oxide polymers (metal oxide in the jargon) but a lot of photons are wasted by passing through the resist (which is comparable in thickness to the pellicle - one we want to absorb, one to transmit). If photons are wasted we get to a problem of stochastics, where there are so few photons per square nm that the edges of patterns become fuzzy and unreliable.
So, work on increasing source power keeps on advancing, it is one of the few levers with no proven limit (although progress is quite slow). It already takes about a megawatt to run the lasers...
Detritus on the pellicle is not a problem because it is out of focus. The system will be no less clean before, so particles will be rare, and a particle in focus on the mask is far more trouble than the same thing a few millimeters above the mask.
There are quite a few physical constrains for increasing the power of an Litho EUV source, from cooling requirements all the way to the reliability of components (doubling the power but halving the uptime will leave you exactly were you started) and the actual space available in a Fab.
If money and space is no object then the ultimate EUV light source would be a km-long Billion dollar Free Electron Laser.
@arsensica Thanks for these answers, really helps me think about particles and pellicles.
I seem to recall IBM Research playing with particle accelerators for EUV a while ago. And I know that the Cyclotron at Lawrence Berkeley Labs was promoting their use in nano scale fabrication. In early 2000s a friend of mine showed me around the place when he was running an experiment there. The "Advanced Light Source" was maybe a European taken that approach.
LBNL is still doing EUV work today. Mostly R&D testing materials, masks and photoresists for suppliers focusing on the upcoming high Numerical Aperture EUV scanner.
Although some of the work they used to do has transitioned to the use of ASML´s EUV scanners in fabs and dedicated EUV inspection tools.
1) Higher EUV energy is necessary to avoid photon noise, since EUV photons are higher power, you actually get fewer photons in a beam than if it was regular 193nm , and that would mean you risk some exposures going bad. Usually it's a tradeoff between high light source power (more photons at once) or longer exposure (more photons over time), and longer exposures bring their own issues (on top of being slow) 2) Depends on the "particle". If it's an organic that can be removed with a bit of ultra-pure water or alcohol, probably can clean the bare mask without damage. If that particle is metal that is now fused to the surface due to either melting (remember, these things get very hot, enough that the robots handling them are made partially of molybdenum or even pure quartz to prevent things from melting) or essentially electroplating themselves on (high energy photons make metals essentially act like solar panels), then you can't remove it without damaging the mask (which is nanometer to micron thick metal itself),
im still waiting for intel or TSMC to walk us through creating silicon, to making a chip every step of the way. I know it was shown at I think 40/28nm but it would be nice to see 22nm or a 14nm chip being produced. I kinda get what they talk about here, but its hard to understand if you are not an cpu maker lol
AT did a long article on semiconductor fabrication a few years ago. I found it rather confusing, but maybe that's just me.
I tried to turn to books on the subject, but the smallest process tech I could find discussed in detail was a book called: "Silicon Processing for the VLSI Era: Deep-Submicron Process Technology Vol. 4". I haven't read it through yet, but it appears to handle 130nm and larger processes.
If anyone knows about serious learning materials for smaller nodes, like 14nm-3nm, I'd appreciate a link or reference.
Process hasn't really changed all that much from the micron scale days. It's basically just mask, dope, clean, mask,deposit, clean, mask, etch, clean, and repeat , just that the number of layers are increased, mask resolution increased, and doping/deposit materials are newer. Other than using smaller wavelengths and more exotic deposit and dope materials, equipment is pretty much unchanged from 20 years ago.
Do you say this as someone who works in the field or is this just your perspective from 10,000ft?
I ask this because I've heard talks by people (e.g. Forrest Norrod), who know what goes into CPUs these days and they indicate that things have changed significantly (at least at the transistor level, if not in the fabrication process and materials themselves), to enable CPUs to get up to the GHz speeds that they do.
In a very basic sense the processes remain similar but as soon as you get to any detailed analysis it no longer holds true.
For example the Chemical Vapor Deposition processes from the 80´s are only in a superficial sense similar to the Atomic Layer Deposition processes of today.
"Do you say this as someone who works in the field or is this just your perspective from 10,000ft?" Third option: someone who works on the equipment used by fabs. You'll never hear from someone that actually works at a fab engineering department since fab secrecy is usually more important than yields or broken machines, but I've been to both fabs and equipment manufacturers in the US and Asia.
You would be surprised how the old the design age is on an average piece of hardware even in a 7nm fab, 28nm and older processes typically run exclusively on devices that have components that went end of life decades ago (Intel's 386 processor is a pretty prime example that is extensively used throughout the industry for industrial PC controller boards, last one was taped out in the mid 2000s, yet even 7nm fabs use machines that run on those chips)
According to the damages supposedly caused by power outages at various foundries, can be several weeks. Modern chips have have multiple layers, and go through many (I believe up to and over 50) coating, exposure, etching and wash/rinse cycles. That's why these power outages are so bad; you basically also have to toss the wafers that were close to their last cycle, which apparently can be three weeks in from the start.
Turn around times for memory are weeks (3-6, depending on how many stacked layers there are), and for SoC parts it is more like 3 months plus whatever delays in testing and packaging add to it.
"In addition, the pellicle needs to be strong to be suspended over a large area of the mask.." How strong can a 50 nm thick membrane possibly be? The thinnest rice paper that can be made is about a micron (or μm) thick. That is 1/1000th of a mm or 1 millionth of a meter. These papers are so thin they are semi-transparent. These pellicles are 20 times thinner; so if you stack 20 of them on top of each other (assuming no air gaps at all) you get the same thickness as that super thin rice paper.
On top of needing to be strong despite being so thin they also need to be so rigid and thermally stable to withstand temperatures of 600 ºC or more and then back to room temperatures without breaking or deforming. I wonder how many such cycles they can endure and how expendable they are. If the precious EUV photomasks cost $300,000 a pop do their pellicles cost a couple of thousand bucks each or more (or less)?
Commercial gold leaf is around 100nm, so 50nm ultra-thin films are not unreasonable. Paper is a terrible analogue as it is a fibrous composite, not a bulk material .
Paper is indeed a terrible analogue; while gold leaf can get so thin it is super fragile at such thickness, so I am not sure if it is a much better analogue. It also does not behave well with wide temperature changes due to a relatively high thermal expansion coefficient (~6 times higher than silicon).
I wonder if this sort of thing is behind the delay of AMD and nVidia GPUs ramping up for volume production. This shortage surely isn't because the globe has gone nuts over $600-$1500 GPUs...;) Those markets are small to begin with. My feeling is that the shortage is caused by poor yields at both FABs--it's as if they are waiting on something to happen before they begin to fill even the limited demand for these GPUs. I just wish AMD, especially, would come clean about the product shortage and stop with the "miner & unprecedented demand" cover ups. The demand cannot be "unprecedented" for a variety of reasons. 1) GPUs have never before cost this much, even @ their MSRPs--so there's no previous demand pattern to evaluate beyond "small" or even "tiny." 2) There has been no evidence in the last several months that either AMD or nVidia has been able to satisfy an "unprecedented demand" in any way, shape, or form. Everywhere you care to look for months all the sources are bare--bone dry--no AIB cards are being sold using either company's GPUs--nothing at the AMD store and nVidia has apparently stopped making its FE editions! There are none on Best Buy at all. It would be nice to hear a little honesty from both companies--the little trickle of these GPUs that has been produced and sold is far less than even normal new-GPU launches expect. Got to be serious yield problems slowing everything to a dead crawl.
According to the youtube'r, moores law is dead, AMD has shipped over 500,000 5000 series CPUs. That sounds like an impressive demand to me. Esp. in Q1. Normally, according to the charts we see for company profits, it's a rather quiet first few months.
The hidden secret is that EUV or even multiple patterning is not needed for increase density of chips. Main reason for disturbing (by diffraction rings) images are combination vawelength of light and density of features on mask. Increasing density of chips require decreasing vawelength of light, or increasing size of masks. First method (EUV) proved to be very difficult, while handling operate larger mask also have its disadvantages (reduced throughput) but overall is much easier. This is reason is why EUV was chosen, serious profits can be made by solving tougher problems. Making chips is business overall, and everyone involved want his money.
Wait, are you claiming making denser chips would have been possible in a more efficient, cheaper way than wit euv but to make one company rich (ASML) everybody in the industry including struggling intel and the Chinese companies desperate to get into cutting edge cpu designs all decided to ignore this cheap possibility and instead spent hundreds of billions on EUV? Sure, sounds totally legit, that is absolutely how capitalism works - leaving opportunities for massive profit on the floor to help another company.
Yeah, I was confused by that take too. Intel tried really hard to hold back on EUV and they've very clearly paid the price, so something tells me it's not quite as simple as "larger mask".
I talk about law of physics here. Creating tools with large masks philosophy, probably require long and large investments, and nobody want to risk money. Beside of this there is 'common sense', kind of belief that only one way will work best, until someone prove otherwise.
If Intel is using single CPU reticles (at least for its larger CPU dies) does that not imply a slower throughput in the masking step ? Is this single CPU reticle due to some other constraint in Intel's tool chain making it difficult for Intel to produce (or use) a larger reticle ?
A separate note - Intel says that it is going to invest $20 billion in 2 new fabs - TSMC is going to invest $100 billion over the next 3 years.
"If Intel is using single CPU reticles (at least for its larger CPU dies) does that not imply a slower throughput in the masking step ?"
More likely it just means the bottleneck is elsewhere, likely energy density, and it's just that Intel and other makers have different approaches to the same problem. If you need X joules/mm^2 to properly expose a mask, and your lamp is y watts, you can do one of two things: 1) Make a smaller mask, focus those Y watts into Z mm^2 for T=X*Z/Y seconds 2) Make a larger mask, focus those Y watts into 4*Z mm^2 for T=4*X*Z/Y seconds
In the end, your patterns/second is unchanged since your actual bottleneck is the source power. Of course there are other factors like: * Single masks are easier to position because your stacking tolerance is actually smaller * Multimasks are faster to position since you only need one move every 4 patterns * Single masks improve yields for multiple layers due to positioning * Multimasks improve yields because one bad pattern only removes that many chips from yield * Single mask reticles are cheaper to make since substrate is smaller and pattern larger (usually) * Multimasks have longer usability period since multiple flaws are less likely to be on the same pattern (and so on)
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ballsystemlord - Wednesday, March 31, 2021 - link
@AntonMaybe you could also point us to some papers!
What's the advantage to higher powered EUV light sources? If you can cause the photomask film to react with lower power why go higher?
Also, if a particle falls onto a pellicle, how do the chip makers remove the particle? Why does the method not work for the bare masks?
Thanks!
FrankSchwab - Wednesday, March 31, 2021 - link
OK, I'm not a semiconductor engineer, but I play one on TV. Here's my take:1. High-powered EUV sources mean shorter exposure times, which means that you process more wafers per hour and make more money.
2. Same answer.
3. Probably initially with a clean gas spray, if that doesn't work then perhaps a clean water or solvent wash. All of which takes time and labor and has a chance of doing more damage. Note that time and labor reduces the number of wafers you can process per hour, and thus how much money you can make.
4. The Pellicle likely has a much tougher, smoother surface. The mask is likely much more easily damaged as a result.
The problem is that you could destroy many, many wafers before you noted that there was a particle. The easiest way to detect a fault is when the wafer is completely processed (all 25-50 layers exposed, developed, etched, etc) and you can test it - but that could be two to three weeks after you started processing the wafer. In the meantime, you might have hundreds or thousands of wafers that are in various stages of processing, and all of them might have the fault.
The harder way to detect a fault is to try to image the wafer after each step, and see if you can detect the fault - but that would likely be very difficult and time-consuming considering that features sizes are on the order of 10 nm. What color of light would you need to resolve such a feature? An even harder way would likely be to try to image the mask and see if you can detect the fault. Imaging anything is going to take time, which will reduce the number of wafers you can process an hour, which is going to reduce the amount of money you make.
Arsenica - Wednesday, March 31, 2021 - link
Regarding 3, Pellicles simply do not need to be cleaned as soon as a particle falls on them as said particle is out-of-focus with the mask/mirrors/light source. Depending on its specific structural characteristics an EUV pellicle could be impossible to clean so a better approach it's to just replace it with a new one.There are inspection tools that can detect defects in the photoresist as soon as the wafer is out of the track. If a defect is detected the photoresist is just stripped and the wafer is exposed again (after correcting the cause of the defect if using the same scanner).
Modern semiconductor manufacturing would be impossible if they had to wait for a wafer to be completely processed before testing it.
TanjB - Wednesday, March 31, 2021 - link
As Frank said the primary goal is throughput.A lot of work has gone into improving the absorption of the EUV by the resist on the target, the current best are tin oxide polymers (metal oxide in the jargon) but a lot of photons are wasted by passing through the resist (which is comparable in thickness to the pellicle - one we want to absorb, one to transmit). If photons are wasted we get to a problem of stochastics, where there are so few photons per square nm that the edges of patterns become fuzzy and unreliable.
So, work on increasing source power keeps on advancing, it is one of the few levers with no proven limit (although progress is quite slow). It already takes about a megawatt to run the lasers...
Detritus on the pellicle is not a problem because it is out of focus. The system will be no less clean before, so particles will be rare, and a particle in focus on the mask is far more trouble than the same thing a few millimeters above the mask.
Arsenica - Wednesday, March 31, 2021 - link
There are quite a few physical constrains for increasing the power of an Litho EUV source, from cooling requirements all the way to the reliability of components (doubling the power but halving the uptime will leave you exactly were you started) and the actual space available in a Fab.If money and space is no object then the ultimate EUV light source would be a km-long Billion dollar Free Electron Laser.
watersb - Thursday, April 1, 2021 - link
@arsensica Thanks for these answers, really helps me think about particles and pellicles.I seem to recall IBM Research playing with particle accelerators for EUV a while ago. And I know that the Cyclotron at Lawrence Berkeley Labs was promoting their use in nano scale fabrication. In early 2000s a friend of mine showed me around the place when he was running an experiment there. The "Advanced Light Source" was maybe a European taken that approach.
Arsenica - Thursday, April 1, 2021 - link
LBNL is still doing EUV work today. Mostly R&D testing materials, masks and photoresists for suppliers focusing on the upcoming high Numerical Aperture EUV scanner.Although some of the work they used to do has transitioned to the use of ASML´s EUV scanners in fabs and dedicated EUV inspection tools.
basroil - Wednesday, March 31, 2021 - link
1) Higher EUV energy is necessary to avoid photon noise, since EUV photons are higher power, you actually get fewer photons in a beam than if it was regular 193nm , and that would mean you risk some exposures going bad. Usually it's a tradeoff between high light source power (more photons at once) or longer exposure (more photons over time), and longer exposures bring their own issues (on top of being slow)2) Depends on the "particle". If it's an organic that can be removed with a bit of ultra-pure water or alcohol, probably can clean the bare mask without damage. If that particle is metal that is now fused to the surface due to either melting (remember, these things get very hot, enough that the robots handling them are made partially of molybdenum or even pure quartz to prevent things from melting) or essentially electroplating themselves on (high energy photons make metals essentially act like solar panels), then you can't remove it without damaging the mask (which is nanometer to micron thick metal itself),
nunya112 - Wednesday, March 31, 2021 - link
im still waiting for intel or TSMC to walk us through creating silicon, to making a chip every step of the way. I know it was shown at I think 40/28nm but it would be nice to see 22nm or a 14nm chip being produced. I kinda get what they talk about here, but its hard to understand if you are not an cpu maker lolballsystemlord - Wednesday, March 31, 2021 - link
AT did a long article on semiconductor fabrication a few years ago. I found it rather confusing, but maybe that's just me.I tried to turn to books on the subject, but the smallest process tech I could find discussed in detail was a book called: "Silicon Processing for the VLSI Era: Deep-Submicron Process Technology Vol. 4". I haven't read it through yet, but it appears to handle 130nm and larger processes.
If anyone knows about serious learning materials for smaller nodes, like 14nm-3nm, I'd appreciate a link or reference.
Thanks!
ballsystemlord - Wednesday, March 31, 2021 - link
Here it is: https://www.anandtech.com/show/8223/an-introductio...watersb - Thursday, April 1, 2021 - link
Cool, thanks for the link!Here also is an often-cited talk from 2012 by Anders Gofas on fab tech, "Indistinguishable from Magic"
https://youtu.be/NGFhc8R_uO4
basroil - Thursday, April 1, 2021 - link
Process hasn't really changed all that much from the micron scale days. It's basically just mask, dope, clean, mask,deposit, clean, mask, etch, clean, and repeat , just that the number of layers are increased, mask resolution increased, and doping/deposit materials are newer. Other than using smaller wavelengths and more exotic deposit and dope materials, equipment is pretty much unchanged from 20 years ago.ballsystemlord - Thursday, April 1, 2021 - link
Do you say this as someone who works in the field or is this just your perspective from 10,000ft?I ask this because I've heard talks by people (e.g. Forrest Norrod), who know what goes into CPUs these days and they indicate that things have changed significantly (at least at the transistor level, if not in the fabrication process and materials themselves), to enable CPUs to get up to the GHz speeds that they do.
Arsenica - Thursday, April 1, 2021 - link
In a very basic sense the processes remain similar but as soon as you get to any detailed analysis it no longer holds true.For example the Chemical Vapor Deposition processes from the 80´s are only in a superficial sense similar to the Atomic Layer Deposition processes of today.
basroil - Friday, April 2, 2021 - link
"Do you say this as someone who works in the field or is this just your perspective from 10,000ft?"Third option: someone who works on the equipment used by fabs. You'll never hear from someone that actually works at a fab engineering department since fab secrecy is usually more important than yields or broken machines, but I've been to both fabs and equipment manufacturers in the US and Asia.
You would be surprised how the old the design age is on an average piece of hardware even in a 7nm fab, 28nm and older processes typically run exclusively on devices that have components that went end of life decades ago (Intel's 386 processor is a pretty prime example that is extensively used throughout the industry for industrial PC controller boards, last one was taped out in the mid 2000s, yet even 7nm fabs use machines that run on those chips)
ballsystemlord - Friday, April 2, 2021 - link
Wow! Thanks!Lux88 - Thursday, April 1, 2021 - link
How much time does it take from clean silicon wafer to raw chip (without package) for a DDR4 chip and latest Snapdragon SoC? A day? 4 days? 2 weeks?eastcoast_pete - Thursday, April 1, 2021 - link
According to the damages supposedly caused by power outages at various foundries, can be several weeks. Modern chips have have multiple layers, and go through many (I believe up to and over 50) coating, exposure, etching and wash/rinse cycles. That's why these power outages are so bad; you basically also have to toss the wafers that were close to their last cycle, which apparently can be three weeks in from the start.FullmetalTitan - Thursday, April 1, 2021 - link
Turn around times for memory are weeks (3-6, depending on how many stacked layers there are), and for SoC parts it is more like 3 months plus whatever delays in testing and packaging add to it.Santoval - Thursday, April 1, 2021 - link
"In addition, the pellicle needs to be strong to be suspended over a large area of the mask.."How strong can a 50 nm thick membrane possibly be? The thinnest rice paper that can be made is about a micron (or μm) thick. That is 1/1000th of a mm or 1 millionth of a meter. These papers are so thin they are semi-transparent. These pellicles are 20 times thinner; so if you stack 20 of them on top of each other (assuming no air gaps at all) you get the same thickness as that super thin rice paper.
On top of needing to be strong despite being so thin they also need to be so rigid and thermally stable to withstand temperatures of 600 ºC or more and then back to room temperatures without breaking or deforming. I wonder how many such cycles they can endure and how expendable they are. If the precious EUV photomasks cost $300,000 a pop do their pellicles cost a couple of thousand bucks each or more (or less)?
edzieba - Thursday, April 1, 2021 - link
Commercial gold leaf is around 100nm, so 50nm ultra-thin films are not unreasonable. Paper is a terrible analogue as it is a fibrous composite, not a bulk material .Santoval - Thursday, April 1, 2021 - link
Paper is indeed a terrible analogue; while gold leaf can get so thin it is super fragile at such thickness, so I am not sure if it is a much better analogue. It also does not behave well with wide temperature changes due to a relatively high thermal expansion coefficient (~6 times higher than silicon).shabby - Thursday, April 1, 2021 - link
Intel: hello asml... we'd like to order some pellicles to boost our 10nm chip yieldsAsml: oh I get it, April fools 🤣
WaltC - Thursday, April 1, 2021 - link
I wonder if this sort of thing is behind the delay of AMD and nVidia GPUs ramping up for volume production. This shortage surely isn't because the globe has gone nuts over $600-$1500 GPUs...;) Those markets are small to begin with. My feeling is that the shortage is caused by poor yields at both FABs--it's as if they are waiting on something to happen before they begin to fill even the limited demand for these GPUs. I just wish AMD, especially, would come clean about the product shortage and stop with the "miner & unprecedented demand" cover ups. The demand cannot be "unprecedented" for a variety of reasons. 1) GPUs have never before cost this much, even @ their MSRPs--so there's no previous demand pattern to evaluate beyond "small" or even "tiny." 2) There has been no evidence in the last several months that either AMD or nVidia has been able to satisfy an "unprecedented demand" in any way, shape, or form. Everywhere you care to look for months all the sources are bare--bone dry--no AIB cards are being sold using either company's GPUs--nothing at the AMD store and nVidia has apparently stopped making its FE editions! There are none on Best Buy at all. It would be nice to hear a little honesty from both companies--the little trickle of these GPUs that has been produced and sold is far less than even normal new-GPU launches expect. Got to be serious yield problems slowing everything to a dead crawl.ballsystemlord - Thursday, April 1, 2021 - link
According to the youtube'r, moores law is dead, AMD has shipped over 500,000 5000 series CPUs.That sounds like an impressive demand to me. Esp. in Q1. Normally, according to the charts we see for company profits, it's a rather quiet first few months.
Spunjji - Friday, April 2, 2021 - link
"I just wish AMD, especially, would come clean about the product shortage and stop with the "miner & unprecedented demand" cover ups."You're asking them to lie to flatter your inaccurate take on the situation. Not gonna happen.
Tomatotech - Thursday, April 1, 2021 - link
Now this is proper *science*. I love this kind of reporting.It's a crying shame we don't get material like this coming out of Intel. They can fuck right off with their 'How wonderful gets done' PR materials.
TristanSDX - Friday, April 2, 2021 - link
The hidden secret is that EUV or even multiple patterning is not needed for increase density of chips. Main reason for disturbing (by diffraction rings) images are combination vawelength of light and density of features on mask. Increasing density of chips require decreasing vawelength of light, or increasing size of masks. First method (EUV) proved to be very difficult, while handling operate larger mask also have its disadvantages (reduced throughput) but overall is much easier. This is reason is why EUV was chosen, serious profits can be made by solving tougher problems. Making chips is business overall, and everyone involved want his money.jospoortvliet - Friday, April 2, 2021 - link
Wait, are you claiming making denser chips would have been possible in a more efficient, cheaper way than wit euv but to make one company rich (ASML) everybody in the industry including struggling intel and the Chinese companies desperate to get into cutting edge cpu designs all decided to ignore this cheap possibility and instead spent hundreds of billions on EUV? Sure, sounds totally legit, that is absolutely how capitalism works - leaving opportunities for massive profit on the floor to help another company.🦁
Spunjji - Friday, April 2, 2021 - link
Yeah, I was confused by that take too. Intel tried really hard to hold back on EUV and they've very clearly paid the price, so something tells me it's not quite as simple as "larger mask".TristanSDX - Friday, April 2, 2021 - link
I talk about law of physics here. Creating tools with large masks philosophy, probably require long and large investments, and nobody want to risk money. Beside of this there is 'common sense', kind of belief that only one way will work best, until someone prove otherwise.Duncan Macdonald - Friday, April 2, 2021 - link
If Intel is using single CPU reticles (at least for its larger CPU dies) does that not imply a slower throughput in the masking step ?Is this single CPU reticle due to some other constraint in Intel's tool chain making it difficult for Intel to produce (or use) a larger reticle ?
A separate note - Intel says that it is going to invest $20 billion in 2 new fabs - TSMC is going to invest $100 billion over the next 3 years.
basroil - Friday, April 2, 2021 - link
"If Intel is using single CPU reticles (at least for its larger CPU dies) does that not imply a slower throughput in the masking step ?"More likely it just means the bottleneck is elsewhere, likely energy density, and it's just that Intel and other makers have different approaches to the same problem. If you need X joules/mm^2 to properly expose a mask, and your lamp is y watts, you can do one of two things:
1) Make a smaller mask, focus those Y watts into Z mm^2 for T=X*Z/Y seconds
2) Make a larger mask, focus those Y watts into 4*Z mm^2 for T=4*X*Z/Y seconds
In the end, your patterns/second is unchanged since your actual bottleneck is the source power. Of course there are other factors like:
* Single masks are easier to position because your stacking tolerance is actually smaller
* Multimasks are faster to position since you only need one move every 4 patterns
* Single masks improve yields for multiple layers due to positioning
* Multimasks improve yields because one bad pattern only removes that many chips from yield
* Single mask reticles are cheaper to make since substrate is smaller and pattern larger (usually)
* Multimasks have longer usability period since multiple flaws are less likely to be on the same pattern
(and so on)