Interconnect
Update 07/02: Albeit a couple of days later than expected, the PCI-SIG has announced this morning that the PCI Express draft 0.71 specification has been released for member review. Following a minimum 30 day review process, the group will be able to publish the draft 0.9 version of the specficiation, putting them on schedule to release the final version of the spec this year. Originally Published 05/25 As part of their yearly developer conference, the PCI Special Interest Group (PCI-SIG) also held their annual press briefing today, offering an update on the state of the organization and its standards. The star of the show, of course, was PCI Express 6.0, the upcoming update to the bus standard that will once again double its data transfer rate...
Using a PCIe Slot to Install DRAM: New Samsung CXL.mem Expansion Module
In the computing industry, we’ve lived with PCIe as a standard for a long time. It is used to add any additional features to a system: graphics, storage, USB...
47 by Dr. Ian Cutress on 5/11/2021
PCIe 6.0 Specification Hits Version 0.5: On Track for 2021
PCI-SIG has released version 0.5 of the PCIe 6.0 specification to its members this week. The new, "first draft" version of the spec includes the feedback the group got...
74 by Anton Shilov on 2/21/2020
SK Hynix Licenses DBI Ultra Interconnect for Next-Gen 3DS and HBM DRAM
SK Hynix has inked a new broad patent and technology licensing agreement with Xperi Corp. Among other things, the company licensed the DBI Ultra 2.5D/3D interconnect technology developed by...
9 by Anton Shilov on 2/11/2020
An Interconnected Interview with Intel’s Ramune Nagisetty: A Future with Foveros
I’ve constantly stated for the last two years that the next battleground in performance for the semiconductor market is going to be in the interconnect – whether we’re speaking...
19 by Dr. Ian Cutress on 1/3/2020
Rambus Unveils PCIe 5.0 Controller & PHY
Rambus has developed a comprehensive PCIe 5.0 and CXL interface solution for chips built using 7 nm process technologies. The interface is now available for licensing by SoC designers...
17 by Anton Shilov on 11/13/2019
Synopsys Demonstrates CXL and CCIX 1.1 over PCIe 5.0: Next-Gen In Action
Synopsys, one of the leading developers of chip development tools and silicon IP, demonstrated its CXL over PCIe 5.0 as well as CCIX 1.1 over PCIe 5.0 solutions at...
5 by Anton Shilov on 10/11/2019
Intel Starts to Close Omni-Path: OPA1 Xeon CPUs on EOL, OPA2 Axed
Intel this week announced plans to discontinue its 1st Generation Xeon Scalable processors with Omni-Path interconnect a year from now. With no 2nd Generation Xeon Scalable products announced to...
9 by Anton Shilov on 10/10/2019
Gen-Z PHY Specification 1.1 Published: Adds PCIe 5.0, Gen-Z 50G Fabric
The Gen-Z Consortium this week released Physical Layer Specification 1.1 for Gen-Z interconnects. The new standard adds enhanced support for PCIe Gen 5 as well as Gen-Z 50G Fabric...
8 by Anton Shilov on 10/4/2019
CXL Consortium Formally Incorporated, Gets New Board Members & CXL 1.1 Specification
Over four years ago, Intel started to develop what is now known as Compute Express Link (CXL), an interface to coherently connect CPUs to all types of other compute...
5 by Anton Shilov on 9/20/2019
Arm Joins CXL Consortium
Arm has officially joined the Compute Express Link (CXL) Consortium in a bid to enable its customers to implement the new CPU-to-Device interconnect and contribute to the specification. Arm...
7 by Anton Shilov on 9/13/2019
Hot Chips 31 Live Blogs: Gen-Z Chipset for Exascale Fabric
One of the key competing interconnects of the future is Gen-Z, and Hewlett Packard Enterprise have a Gen-Z chipset to show at Hot Chips today.
5 by Dr. Ian Cutress on 8/20/2019
AMD Joins CXL Consortium: Playing in All The Interconnects
AMD's CTO, Mark Papermaster, has published a blog post this week said that AMD has joined the Compute Express Link (CXL) Consortium. The industry group is led by a...
43 by Anton Shilov on 7/19/2019
Compute Express Link (CXL): From Nine Members to Thirty Three
Last month the CXL Specification 1.0 was released as a future cache coherent interconnect that uses the PCIe 5.0 physical infrastructure but aimed to provide a breakthrough in utility...
18 by Dr. Ian Cutress on 4/15/2019
CXL Specification 1.0 Released: New Industry High-Speed Interconnect From Intel
With the battleground moving from single core performance to multi-core acceleration, a new war is being fought with how data is moved around between different compute resources. The Interconnect...
48 by Ian Cutress on 3/11/2019
Gen-Z Interconnect Core Specification 1.0 Published
The first major release of the Gen-Z systems interconnect specification is now available. The Gen-Z Consortium was publicly announced in late 2016 and has been developing the technology as...
23 by Billy Tallis on 2/13/2018
Gen-Z Consortium Formed: Developing a New Memory Interconnect
Anyone tasked with handling the way data is moved around a processor deserves praise. It takes time, dedication and skill to design something that not only works appropriately and...
15 by Ian Cutress on 10/12/2016
Arteris Announces Ncore Cache-Coherent Interconnect
Arteris is a little mentioned company which we haven't had the opportunity to cover in the past, yet they provide IP for one of the most important parts of...
9 by Andrei Frumusanu on 5/24/2016
ARM Announces New CCI-550 and DMC-500 System IPs
Today ARM announces two new additions to its CoreLink system IP design portfolio, the CCI-550 interconnect and DMC-500 memory controller. Starting off with the CCI announcement, we find the...
5 by Andrei Frumusanu on 10/27/2015
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