Most of this is abit over my head. If possible maybe next time use literary devices to explain these technologies. Also what about tsv and stacked dice?
It isn't an easy concept to grasp at first. Transistors generally operate in two states. On and off. They require a certain voltage to make them come on. For the sake of simplicity, these two states are 1's and 0's (data bits). They form logic gates in circuits (if this and this or this then it equals this). The material that they use for transistors (and diodes) are silicon. Silicon requires approximately .7 volts to forward bias (allow current to flow and turn on). There are literally thousands of websites and graphic representations of basic transistor theory to explore. Try "How Stuff Works dot com".
Just took a quick look at the article for now so maybe i've missed it but i don't think you mention 3D at all (actual 3D not FinFET or 2.5D packaging). And here comes the crazy question, was looking at the CMOS Chip Structure pic and wondered if anyone has tried to make curved (on 1 or even 2 axis) chips just to have more room on the extremal layers. As i wrote this i remembered the Sony curved image sensor and i wonder how would they fab that if they actually make it into a real product.Any clue?
Curving the wafer actually has major impacts on electronic operation. For example wafer bending is currently done by implanting Germanium into the wafer for PFETs. Because Ge is larger than Si, this causes the wafer to bend. This bend increases hole mobility making PFETs more conductive and faster, but slows down NFETs, thus manufacturers implant Ge only at PFET locations. This processes of bending the wafer by implanting Ge is strained silicon, and 1st started showing up around the 130nm era. It is done because for similarly sized transistors, NFETs are around 2.7x more conductive than PFETs without strained silicon.
There is definitely no curving or any wafer. Ge is used to strain the silicon crystal latice. Ge is in the same group on the periodic table and forms the same diamond cubic crystal structure. Grading a fraction of Ge (larger atoms longer bond lengths) into the Silicon latice the silicon bonds effectively get stretched (see image in article). This has a physical effect on the mobility of electrons and holes. Curving a wafer is a non-starter as NONE of the standard processing techniques would work...wafers have to be not only flat but ultra flat for litho optics, dry etch, wet etch spinners, ion implanters...
When you hear 22nm, 32nm, 16nm, etc the number you are hearing is the smallest feature size that can be imprinted via lithography. This is not necessarily the smallest feature size than can be implemented on the process.
This is not true. Node size was loosely defined as the half pitch of either the poly-silicon gate or the tightest metal pitch. The node size designation however, has not followed the minimum half pitch for many technologies, from any of the fabs. Node size is now a purely marketing term. If a fab were to implement HKMG, strained silicon...these things would not necessarily have any effect on the dimensions of transistors but they would result in improvements to the chip performance. Density is only 1 component that plays into node designation these days and even then density of the transistors is being tightened by some fabs while leaving the density of the upper layers unchanged.
Again just because lithographic features can be made a certain size does not mean you make everything that size. Maybe there is just one minor feature that is really that size. I'm saying that process size is the minimum size that can cut by the ebeam into a lithography mask and transferred if the design calls for it. This is why when looking at a processor that the feature size is so hard to quantify. Just one feature at whatever they advertise can let them call it that number. Yes feature size doesn't need to have anything to do with density or performance and is mostly a marketing thing.
There's probably something to be said about breezing through this(of my own free will moreover), while having such a hard time with the exact same material from the textbook. Go figure.
I am wondering if we haven't already hit the limits of current technology. TSMC doesn't seem to be able to produce anything more powerful than a SOC for phones and tablets on their 20nm process. While Intel seems to think they will have 14nm desktop and notebook parts out in the second quarter of next year, I wonder if they really will. Right now all we have seen from them at 14nm is similar to what TSMC is able to do at 20nm.
This really concerns me as far as technology stagnating until the next big thing comes along.
There's no end in sight. About a year ago, perhaps a little earlier, the 7 or 5nm nodes were seen as the end of Moore's Law. Advancements have been made since then, though, and scaling past the 5nm node is very likely. 10nm's "recipe" is basically all finished at Intel at this point, with "all" that's left to do at this point being increasing the yields. EUV is making good progress, finally, and should be ready for insertion at Intel's 7nm node (if they skipped it for 10nm, which they likely did).
14nm has been in production for quite some time now, with Broadwell first landing in tablets later this month. The chances that Broadwell won't make it to the desktop and notebook market around the middle of next year are essentially zero.
We're still also on schedule to have 450mm wafers introduced by the end of the decade, which would reduce costs by ~30%.
Even not looking at Intel, TSMC has millions of 20nm-based products on the market right now. 20nm is roughly twice as dense as its 28nm predecessor. It doesn't really make sense to be so skeptical of progress, given that the proof pudding has already been delivered.
All those 20nm products are not desktop or notebook CPUs or GPUs, which they lead AMD and Nvidia to believe they would be able to do. Intel is way behind its original estimates to get Broadwell out, and that just in table SOCs. Intel wanted badly to get Broadwell parts out for the new school year, then it was Christmas, now it is Q2 of 2015. Yes, I think there is plenty of reason to be skeptical.
Your facts are all incorrect...If you can produce an SOC you already have all of the capability to produce GPU's or CPU's since it has logic, SRAM and graphics components already. Broadwell parts are already in the hands of vendors NOW and are being sold this year and they are not SOC's they are low power full core chips. 14nm Broadwell chips are in no way equivalent to 20nm TSMC chips. A fab can use the additional capability of a new node in different ways. They can reduce density to make chips cheaper to make, increase performance, decrease power and all of these things will be done in different ratios depending on the product. You need to work on detailed reasoning and apples to apples comparisons.
The problem is that the only real advancements are more expensive per transistor and I doubt they will change.
The great thing about process shrinks is that it reduces the cost per transistor.
Also I doubt EUV will ever work. It has been almost ready and a couple years away for a decade. Tell me when you don't need MW levels of power to get usable light to a wafer and maybe I will consider it.
450mm wafers have also been just a couple years away for at least 15 years. I'll believe the 2020 hype when I actually see it.
The way to the next node is easy and everyone knows they can use triple patterning. Nobody wants that because of the expense is huge already and every single circuit would have to be redrawn due to limitations on the pokygons.
I don't know what's next but the only people expecting EUV to pan out are the people who have spent billions trying to make it work and failing.
The problem with smaller processes is not physically producing them. The problem is that they start getting slower than larger processes. This is due to 2 reasons.
1. Narrower, more resistive interconnects. 2. Increase in channel doping levels due to not having enough dopant atoms to form a P-N junction as processes increase.
1. As process sizes shrink, so do interconnects. Resistance is dependent on cross sectional area and length of the wire. As you shrink a process, the cross sectional area drops at a squared rate, while length drops at a linear rate. The end result is that wires become linearly more resistive as the process shrinks. Keeping wire length down due to resistance is also a big reason why individual core transistor counts have not been going up significantly. The cores need to stay small to keep the wire length down. Repeaters to boost current drive ability on long wires has been around starting at around 90nm.
2. If you want a 10nm process, you probably have a gate length of 10nm. The volume of a 10nm cube is 10^-18 cm^-3. High doping levels are those above around 10^17 atoms per cm. If we take a high doping level of say 10^18 atoms per cm, then we have only one single dopant atom in the entire channel region of the transistor. This means that if you are one atom off, you lose a transistor, which is difficult not to do with over 1B transistors in a microprocessor. You can dope up to around 10^21 cm^-3, but then your electron and hole mobility are terrible. Mobility is directly proportional to how much current a transistor can push, so as mobility drops performance drops. See this link for what happens to mobility as dopant levels increase.
From what I read the problem isn't as much phyiscal or technical feasability as economical viability: Moore's law was mostly about the ability to deliver more power at a lower price for the end consumer pushing the technology. Now the economical yields of process shrinks are diminishing to the point where further shrinks won't pay for themselves.
If you're also interested in how simpler transistors are made; hack-a-day's hosted a video lecture from someone who was producing chips with a handful of transistors on them in her home lab a few years ago.
Graphene isn't dead in the water. There are ways to create a bandgap, for example using bilayer graphene and introducing a gap via electric fields or doping.
Then you can take advantage of its remarkable carrier mobility. Mass production remains a huge issue, and I also have concerns about its effect on living creatures and the environment. http://www.gizmag.com/graphene-bad-for-environment...
The description of the wafer processing is pretty much completely wrong. FEOL line processing involves almost no direct oxide etches. It also completely skips shallow trench isolation and all the CMP steps involved in patterning. The wiring of the chip has no metal etch anymore either. Every metal layer in a modern (<10 years old) logic chip is produced via damascene patterning of copper. (You etch a dielectric, fill the trenches with copper and then polish the copper back.)
Much of the article is definitely quite simplified but the intent is to give a general idea of the process. I'd love to learn about this subject in more depth though.
Could you expand on "the holes in the p-type and the electrons in n-type are all pushed towards the junction, which causes the depletion zone to shrink" a bit? Connecting the + terminal @ the p semiconductor means you'll get electrons flowing into the n semiconductor. This should result in the n semiconductor being even more relatively negative, and the opposite on the p semiconductor. If that's the case, why wouldn't that cause a larger delta V at the junction?
The issue here is that there is a diffusion of charge carriers. The negative end provides the potential that pushes electrons towards the depletion layer on the n-side, which has holes due to the diffusion that was previously discussed. The positive end pushes holes towards the center on the p-side, which has electrons in the depletion region.
Nice piece. It's great to see easily accessible high-level articles being written on micro-nano IC tech. I work for a large foundry, and its often hard to explain to people what's happening inside their devices.
First, a minor typo appears in the High-k / Metal Gate section, 3rd paragraph, 1st sentence: "comlexity" should be "complexity". (Amazing that in an article of this complexity I could only find one typo!)
Second, I noticed that there was no mention of compound semiconductors like GaAs. I was under the impression that while many technical issues have been resolved, it remains prohibitively more expensive than silicon. Is this indeed the case, or are other factors more of an issue than cost?
Great article, by the way, especially in regard to FinFET transistors. Makes things much clearer in my mind.
A lot of them can only make n-type or p-type transistors. While that's not a problem for power or RF transistors; to control energy consumption and heat production you need both types to do CMOS logic gates.
Thank you very much for the much needed and very well written and illustrated introduction!
How long does it take in real life to make a wafer with chips (with or without the testing)? Does it take hours, days or weeks to get a finished wafer with chips from silicon crystal?
At the end you mention a rate of "100+ wafers per hour", but I understand it as "number of wafers we are working on in parallel" rather than "number of wafers from start to finish".
Time depends on the device and fab. Weeks though. I'd guess the average for any given chip(fron latest greatest down to simple microcontrollers) 3-6 weeks in the fab, another couple for testing packaging.
He was talking about replacing a single photo tool(scanner/stepper) that does 100 wafers per hour with ebeam. There can be 10-100 scanners in fab, and as you say working in parallel.
Great article. Our society has poured vast resources into this area at multiple levels and achieved incredible results. I can't help but think that if we had been motivated to put this kind of engineering effort towards space projects we would not only be colonizing Mars by now, but mining asteroids and running orbital solar panels. Maybe we'll eventually come back to these things, with new powers bestowed by this "inner space" technology. Or maybe not.
You missed the biggest reason why SOI has gone out of fashion from microprocessors. Costs and fabrication are not a big deal. All you do is implant O2 deep into the wafer, then heat it to turn the implanted O2 into SiO2. This is 2 extra steps of 400 or so done when processing a wafer. No big deal.
The problem is that there is no more transistor body connection to ground. This means that the body can build up charge like in flash memory. What it ends up doing is skewing the threshold voltage. When doing high voltage work with radio or power electronics with big transistors this is no big deal, but with microprocessors it is a significant. Even worse is this charge depends on the previous state of the transistor and how long it has been in that state, which is difficult to predict, and thus we have unpredictable performance swings with SOI.
This is a PD-SOI issue that falls under history effects mentioned in the article. FD-SOI doesn't have history effects as the body doesn't inherently have mobile charge carriers, which must be generated by band-bending.
So if FD-SOI gets rid of body effects then why is SOI not common? I supposed you can't just implant O2 and anneal for FD-SOI? Is sanding the wafer and growing SiO2 what needs to be done?
The article also mentions temperatures, but the heatsink is attached to the interconnect side of the CPU instead of the bulk side from my understanding so this should have no impact.
The biggest issue continues to be cost. While continuing to push bulk CMOS is more expensive in up-front cost, SOI has much higher fluid costs. There's also only one supplier of SOI wafers to my knowledge. (Soitec)
Modern chips are connected with a C4 process (Controlled Collapse Chip Connect) The interconnect side is down, the bulk side is up. The heatsink is touching the back of the wafer.
Great article for this old EE whose career was mostly in sales and marketing, but who has had a great love for PC's since the days of Apple II and CP/M. Nice that someone has taken the time and effort to give this generalized explanation even if some of the nit-pickers quibble over a typo or some specific detail. Until one has had to actually produce such a piece he/she should refrain from too much criticism. Easy and quick it ain't! Kudos...
After many years of editing scientific / technical / medical journal articles, I tend to see the structural details as well as the informational content.
To me, a typo is like a dead pixel. If it can be removed, it makes the image or storyline that much more immersive and enjoyable to behold.
The purpose is aiding the author in polishing the article to perfection, not fault-finding or nit-picking.
Like many tech enthusiasts, an editor brings a passionate pursuit of excellence to his craft and to his team.
Like many other commenters here, I see myself as making a small contribution, from time to time, to the AnandTech team.
P.S. I have also authored or coauthored numerous articles (and a textbook chapter) in the fields of medical physics and medical imaging, including invited review articles.
So I offer my appeciation and congratulations to Josh Ho for gifting us with an article of such surpassing excellence.
Exactly my thoughts! It's really sad to see how level of this site has dropped significantly over years due to caring for more mindless crowd; certain reviewers doesn't bother to actually understand what they are reviewing and just pushing for faster time to post and more numbers (that are by large part are quite unrelevant).
But articles like this show that hope is not lost here – great job, would love to see more articles like this.
This is what puzzling for a long time: the wavelength of ArF laser is 192nm, the feature size of Core M processor is 14nm or 14 times smaller. With NA=1 you can focus into spot of the Airy size equal approximately to wavelength only. Using phase shift trick you can probably drop that size twice to 96nm. Using nonlinearity of photoresist you can drop twice more or to 49nm. My guess is that using titlting of laser (i do not get how it actually works) they can get 24nm. Adding water you can get 24 / 1.33=18nm. How they get 14nm and sometimes even 10nm what Samsung claims with just the optical lithography?
Over the past 20 years many tricks have been developed to overcome what was originally believed to be an optical limitation. Lithography tools are much more complicated than the brief descriptions given and have had many advances including going from aligners->steppers->scanners, NA=1.35, illumination system improvements, resist improvements, anti-reflective coating improvements, different types of phase shift on all reticles... On top of the fact that we can resolve sub 50nm pitches with 193nm light we use various double patterning schemes.
It's a wonderful article, something I'll quote and link to for a long time very much along the epochal piece Anand wrote on Flash.
I'd like to see a followup or a mention to memristors, though. Not only because they are about to eliminate disk, flash, DRAM and SRAM, but because they also have such huge potential in FPGA and log redesign.
On top their stacking capabilities together with the low energy density and production cost may actually allow attenuating the need for process shrinks to the point where it almost feels as though Moore's law was continuing, but not through process shrinks.
I don't find this an "Intro", but rather like a summary of EE 301 for people who have taken EE 101, EE 201, and EE 301. To me, it assumes a high level to prerequisites. Also, the article could benefit by more care taken to definitions ... for example, EUV is used repeatedly on the fourth page, but not defined until the sixth page.
"But there is far more to be done, as literally everything we write about at AnandTech depends upon ever faster, smaller, and more efficient transistors packed as tightly as possible. Without this continued innovation, the PC, smartphone, and wearables that we see today would be impossible to make."
Thank you. Needed this article to remove the foul taste left my the recent iPhone reviews reasoning the phone is great because it can't improve any more.
Awesome article. Great introduction to people curious about the industry. Some terms were glossed over that might help explain semiconductor physics more such as work function and crystal lattice, but there's only so much you can cover at once
It sounds like electron beam is the best path forward but I have a feeling the bean counters will push for using the nano method because it would create "efficiencies" that shareholders would love. I don't see any mold at that feature size being reusable. It seems like we are approaching a size where we will be lowering energy efficiency due to leakage and limitations it clock speed.
I remember reading about a new type of transistor Intel was working on that required much less voltage, that would be a good next step.
That would be NTV or Near Threshold Voltage. Basically, requires a lot less energy to turn transistors On and Off, which just happens to be the only time they consume energy (not counting leakage)
Great work, Joshua, I still find it a bit too challenging of a read, especially at the chemistry level, but will definitely chew through this in a couple of attempts.
I want to major in electrical engineering (Ihave 7 years to go before I'm finished) and I find this article very interesting but I still can't figure out how you can create logic with the transistors or how do they switch from on to off, is it switching itself when the current is too low/high if I undestood correctly?
OK, take 50nm, with doublepatterning 25. How they get 14 and even 10nm? That needs something else. You can not make 10nm line with 20x longer wavelength
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PrayForDeath - Thursday, October 9, 2014 - link
Articles like this are the reason why I visit Anandtech *starts reading*monstercameron - Thursday, October 9, 2014 - link
Most of this is abit over my head. If possible maybe next time use literary devices to explain these technologies. Also what about tsv and stacked dice?Homeles - Thursday, October 9, 2014 - link
Is there anything in particular you're struggling with?Kutark - Sunday, October 12, 2014 - link
I'm with him. I need someone to take some paper and some crayons and draw me a picture hahaha.climber07 - Monday, October 13, 2014 - link
It isn't an easy concept to grasp at first. Transistors generally operate in two states. On and off. They require a certain voltage to make them come on. For the sake of simplicity, these two states are 1's and 0's (data bits). They form logic gates in circuits (if this and this or this then it equals this). The material that they use for transistors (and diodes) are silicon. Silicon requires approximately .7 volts to forward bias (allow current to flow and turn on). There are literally thousands of websites and graphic representations of basic transistor theory to explore. Try "How Stuff Works dot com".Burn2learn - Friday, November 14, 2014 - link
How can this be over your head if your aware of thru silicon vias (tsv)adityarjun - Thursday, October 9, 2014 - link
Awesome! Hope to see a lot more of such articles for learners.seanleeforever - Thursday, October 9, 2014 - link
pretty much a brief review of my E.E college course back in the days.great article.
A5 - Thursday, October 9, 2014 - link
Yep. Getting bad SRH equation flashbacks now :-pjjj - Thursday, October 9, 2014 - link
Just took a quick look at the article for now so maybe i've missed it but i don't think you mention 3D at all (actual 3D not FinFET or 2.5D packaging).And here comes the crazy question, was looking at the CMOS Chip Structure pic and wondered if anyone has tried to make curved (on 1 or even 2 axis) chips just to have more room on the extremal layers. As i wrote this i remembered the Sony curved image sensor and i wonder how would they fab that if they actually make it into a real product.Any clue?
Khenglish - Thursday, October 9, 2014 - link
Curving the wafer actually has major impacts on electronic operation. For example wafer bending is currently done by implanting Germanium into the wafer for PFETs. Because Ge is larger than Si, this causes the wafer to bend. This bend increases hole mobility making PFETs more conductive and faster, but slows down NFETs, thus manufacturers implant Ge only at PFET locations. This processes of bending the wafer by implanting Ge is strained silicon, and 1st started showing up around the 130nm era. It is done because for similarly sized transistors, NFETs are around 2.7x more conductive than PFETs without strained silicon.EMM81 - Monday, October 13, 2014 - link
There is definitely no curving or any wafer. Ge is used to strain the silicon crystal latice. Ge is in the same group on the periodic table and forms the same diamond cubic crystal structure. Grading a fraction of Ge (larger atoms longer bond lengths) into the Silicon latice the silicon bonds effectively get stretched (see image in article). This has a physical effect on the mobility of electrons and holes. Curving a wafer is a non-starter as NONE of the standard processing techniques would work...wafers have to be not only flat but ultra flat for litho optics, dry etch, wet etch spinners, ion implanters...hlovatt - Thursday, October 9, 2014 - link
Great article. More please!witeken - Thursday, October 9, 2014 - link
Awesome, thanks for the great article.However, 22nm doesn't have a single feature size of 22nm. It's just a name, and so are 28nm, 20nm, 16nm, 14nm,...
For example, the fins of 22nm are 8nm while the gate pitch is 90nm. (http://images.anandtech.com/doci/8367/14nmFeatureS...
Khenglish - Thursday, October 9, 2014 - link
When you hear 22nm, 32nm, 16nm, etc the number you are hearing is the smallest feature size that can be imprinted via lithography. This is not necessarily the smallest feature size than can be implemented on the process.EMM81 - Monday, October 13, 2014 - link
This is not true. Node size was loosely defined as the half pitch of either the poly-silicon gate or the tightest metal pitch. The node size designation however, has not followed the minimum half pitch for many technologies, from any of the fabs. Node size is now a purely marketing term. If a fab were to implement HKMG, strained silicon...these things would not necessarily have any effect on the dimensions of transistors but they would result in improvements to the chip performance. Density is only 1 component that plays into node designation these days and even then density of the transistors is being tightened by some fabs while leaving the density of the upper layers unchanged.Khenglish - Wednesday, October 15, 2014 - link
Again just because lithographic features can be made a certain size does not mean you make everything that size. Maybe there is just one minor feature that is really that size. I'm saying that process size is the minimum size that can cut by the ebeam into a lithography mask and transferred if the design calls for it. This is why when looking at a processor that the feature size is so hard to quantify. Just one feature at whatever they advertise can let them call it that number. Yes feature size doesn't need to have anything to do with density or performance and is mostly a marketing thing.Keisari - Thursday, October 9, 2014 - link
A very necessary article. Great initiative!martixy - Thursday, October 9, 2014 - link
There's probably something to be said about breezing through this(of my own free will moreover), while having such a hard time with the exact same material from the textbook.Go figure.
Murloc - Thursday, October 9, 2014 - link
It's meant to be intuitive and summarized in a limited amount of space. That's why it's easy to read. It has way less depth than a textbook.danjw - Thursday, October 9, 2014 - link
I am wondering if we haven't already hit the limits of current technology. TSMC doesn't seem to be able to produce anything more powerful than a SOC for phones and tablets on their 20nm process. While Intel seems to think they will have 14nm desktop and notebook parts out in the second quarter of next year, I wonder if they really will. Right now all we have seen from them at 14nm is similar to what TSMC is able to do at 20nm.This really concerns me as far as technology stagnating until the next big thing comes along.
Homeles - Thursday, October 9, 2014 - link
There's no end in sight. About a year ago, perhaps a little earlier, the 7 or 5nm nodes were seen as the end of Moore's Law. Advancements have been made since then, though, and scaling past the 5nm node is very likely. 10nm's "recipe" is basically all finished at Intel at this point, with "all" that's left to do at this point being increasing the yields. EUV is making good progress, finally, and should be ready for insertion at Intel's 7nm node (if they skipped it for 10nm, which they likely did).14nm has been in production for quite some time now, with Broadwell first landing in tablets later this month. The chances that Broadwell won't make it to the desktop and notebook market around the middle of next year are essentially zero.
We're still also on schedule to have 450mm wafers introduced by the end of the decade, which would reduce costs by ~30%.
Even not looking at Intel, TSMC has millions of 20nm-based products on the market right now. 20nm is roughly twice as dense as its 28nm predecessor. It doesn't really make sense to be so skeptical of progress, given that the proof pudding has already been delivered.
danjw - Thursday, October 9, 2014 - link
All those 20nm products are not desktop or notebook CPUs or GPUs, which they lead AMD and Nvidia to believe they would be able to do. Intel is way behind its original estimates to get Broadwell out, and that just in table SOCs. Intel wanted badly to get Broadwell parts out for the new school year, then it was Christmas, now it is Q2 of 2015. Yes, I think there is plenty of reason to be skeptical.EMM81 - Monday, October 13, 2014 - link
Your facts are all incorrect...If you can produce an SOC you already have all of the capability to produce GPU's or CPU's since it has logic, SRAM and graphics components already. Broadwell parts are already in the hands of vendors NOW and are being sold this year and they are not SOC's they are low power full core chips. 14nm Broadwell chips are in no way equivalent to 20nm TSMC chips. A fab can use the additional capability of a new node in different ways. They can reduce density to make chips cheaper to make, increase performance, decrease power and all of these things will be done in different ratios depending on the product. You need to work on detailed reasoning and apples to apples comparisons.errorr - Thursday, October 9, 2014 - link
The problem is that the only real advancements are more expensive per transistor and I doubt they will change.The great thing about process shrinks is that it reduces the cost per transistor.
Also I doubt EUV will ever work. It has been almost ready and a couple years away for a decade. Tell me when you don't need MW levels of power to get usable light to a wafer and maybe I will consider it.
450mm wafers have also been just a couple years away for at least 15 years. I'll believe the 2020 hype when I actually see it.
The way to the next node is easy and everyone knows they can use triple patterning. Nobody wants that because of the expense is huge already and every single circuit would have to be redrawn due to limitations on the pokygons.
I don't know what's next but the only people expecting EUV to pan out are the people who have spent billions trying to make it work and failing.
ShieTar - Friday, October 10, 2014 - link
EUV is not "almost ready", it has been commercially available for 2 years now.http://www.zeiss.com/semiconductor-manufacturing-t...
Khenglish - Thursday, October 9, 2014 - link
The problem with smaller processes is not physically producing them. The problem is that they start getting slower than larger processes. This is due to 2 reasons.1. Narrower, more resistive interconnects.
2. Increase in channel doping levels due to not having enough dopant atoms to form a P-N junction as processes increase.
1. As process sizes shrink, so do interconnects. Resistance is dependent on cross sectional area and length of the wire. As you shrink a process, the cross sectional area drops at a squared rate, while length drops at a linear rate. The end result is that wires become linearly more resistive as the process shrinks. Keeping wire length down due to resistance is also a big reason why individual core transistor counts have not been going up significantly. The cores need to stay small to keep the wire length down. Repeaters to boost current drive ability on long wires has been around starting at around 90nm.
2. If you want a 10nm process, you probably have a gate length of 10nm. The volume of a 10nm cube is 10^-18 cm^-3. High doping levels are those above around 10^17 atoms per cm. If we take a high doping level of say 10^18 atoms per cm, then we have only one single dopant atom in the entire channel region of the transistor. This means that if you are one atom off, you lose a transistor, which is difficult not to do with over 1B transistors in a microprocessor. You can dope up to around 10^21 cm^-3, but then your electron and hole mobility are terrible. Mobility is directly proportional to how much current a transistor can push, so as mobility drops performance drops. See this link for what happens to mobility as dopant levels increase.
http://ecee.colorado.edu/~bart/book/mobility.gif
abufrejoval - Saturday, October 11, 2014 - link
From what I read the problem isn't as much phyiscal or technical feasability as economical viability: Moore's law was mostly about the ability to deliver more power at a lower price for the end consumer pushing the technology. Now the economical yields of process shrinks are diminishing to the point where further shrinks won't pay for themselves.DanNeely - Thursday, October 9, 2014 - link
If you're also interested in how simpler transistors are made; hack-a-day's hosted a video lecture from someone who was producing chips with a handful of transistors on them in her home lab a few years ago.http://hackaday.com/2010/03/10/jeri-makes-integrat...
anexanhume - Thursday, October 9, 2014 - link
Graphene isn't dead in the water. There are ways to create a bandgap, for example using bilayer graphene and introducing a gap via electric fields or doping.http://www-als.lbl.gov/index.php/contact/56-bilaye...
Then you can take advantage of its remarkable carrier mobility. Mass production remains a huge issue, and I also have concerns about its effect on living creatures and the environment. http://www.gizmag.com/graphene-bad-for-environment...
dragonsqrrl - Thursday, October 9, 2014 - link
Article like non other, thanks.tarlinian - Thursday, October 9, 2014 - link
The description of the wafer processing is pretty much completely wrong. FEOL line processing involves almost no direct oxide etches. It also completely skips shallow trench isolation and all the CMP steps involved in patterning. The wiring of the chip has no metal etch anymore either. Every metal layer in a modern (<10 years old) logic chip is produced via damascene patterning of copper. (You etch a dielectric, fill the trenches with copper and then polish the copper back.)JoshHo - Thursday, October 9, 2014 - link
Much of the article is definitely quite simplified but the intent is to give a general idea of the process. I'd love to learn about this subject in more depth though.revoltracers - Thursday, October 9, 2014 - link
I am printing this one out.tuxRoller - Thursday, October 9, 2014 - link
Could you expand on "the holes in the p-type and the electrons in n-type are all pushed towards the junction, which causes the depletion zone to shrink" a bit?Connecting the + terminal @ the p semiconductor means you'll get electrons flowing into the n semiconductor. This should result in the n semiconductor being even more relatively negative, and the opposite on the p semiconductor.
If that's the case, why wouldn't that cause a larger delta V at the junction?
JoshHo - Friday, October 10, 2014 - link
The issue here is that there is a diffusion of charge carriers. The negative end provides the potential that pushes electrons towards the depletion layer on the n-side, which has holes due to the diffusion that was previously discussed. The positive end pushes holes towards the center on the p-side, which has electrons in the depletion region.tuxRoller - Friday, October 10, 2014 - link
Damn.IOW, I got my field directions mixed.
Thanks.
dyc4ha - Thursday, October 9, 2014 - link
Thanks! I am still trying to digest this article, but nevertheless I know I am enjoying it! Keep it goingPacificToast - Thursday, October 9, 2014 - link
Nice piece. It's great to see easily accessible high-level articles being written on micro-nano IC tech. I work for a large foundry, and its often hard to explain to people what's happening inside their devices.Dr.Neale - Friday, October 10, 2014 - link
First, a minor typo appears in the High-k / Metal Gate section, 3rd paragraph, 1st sentence: "comlexity" should be "complexity". (Amazing that in an article of this complexity I could only find one typo!)Second, I noticed that there was no mention of compound semiconductors like GaAs. I was under the impression that while many technical issues have been resolved, it remains prohibitively more expensive than silicon. Is this indeed the case, or are other factors more of an issue than cost?
Great article, by the way, especially in regard to FinFET transistors. Makes things much clearer in my mind.
Thanks, Josh.
DanNeely - Friday, October 10, 2014 - link
A lot of them can only make n-type or p-type transistors. While that's not a problem for power or RF transistors; to control energy consumption and heat production you need both types to do CMOS logic gates.JoshHo - Friday, October 10, 2014 - link
While GaAs is popular in MMIC applications, it normally isn't possible to implement CMOS logic with such transistors.Lux88 - Friday, October 10, 2014 - link
Thank you very much for the much needed and very well written and illustrated introduction!How long does it take in real life to make a wafer with chips (with or without the testing)? Does it take hours, days or weeks to get a finished wafer with chips from silicon crystal?
At the end you mention a rate of "100+ wafers per hour", but I understand it as "number of wafers we are working on in parallel" rather than "number of wafers from start to finish".
aicjofs - Friday, October 10, 2014 - link
Time depends on the device and fab. Weeks though. I'd guess the average for any given chip(fron latest greatest down to simple microcontrollers) 3-6 weeks in the fab, another couple for testing packaging.He was talking about replacing a single photo tool(scanner/stepper) that does 100 wafers per hour with ebeam. There can be 10-100 scanners in fab, and as you say working in parallel.
ABR - Friday, October 10, 2014 - link
Great article. Our society has poured vast resources into this area at multiple levels and achieved incredible results. I can't help but think that if we had been motivated to put this kind of engineering effort towards space projects we would not only be colonizing Mars by now, but mining asteroids and running orbital solar panels. Maybe we'll eventually come back to these things, with new powers bestowed by this "inner space" technology. Or maybe not.pepone1234 - Friday, October 10, 2014 - link
This article is amazing!! Thank you for writing this :DKhenglish - Friday, October 10, 2014 - link
You missed the biggest reason why SOI has gone out of fashion from microprocessors. Costs and fabrication are not a big deal. All you do is implant O2 deep into the wafer, then heat it to turn the implanted O2 into SiO2. This is 2 extra steps of 400 or so done when processing a wafer. No big deal.The problem is that there is no more transistor body connection to ground. This means that the body can build up charge like in flash memory. What it ends up doing is skewing the threshold voltage. When doing high voltage work with radio or power electronics with big transistors this is no big deal, but with microprocessors it is a significant. Even worse is this charge depends on the previous state of the transistor and how long it has been in that state, which is difficult to predict, and thus we have unpredictable performance swings with SOI.
JoshHo - Friday, October 10, 2014 - link
This is a PD-SOI issue that falls under history effects mentioned in the article. FD-SOI doesn't have history effects as the body doesn't inherently have mobile charge carriers, which must be generated by band-bending.Khenglish - Friday, October 10, 2014 - link
So if FD-SOI gets rid of body effects then why is SOI not common? I supposed you can't just implant O2 and anneal for FD-SOI? Is sanding the wafer and growing SiO2 what needs to be done?The article also mentions temperatures, but the heatsink is attached to the interconnect side of the CPU instead of the bulk side from my understanding so this should have no impact.
JoshHo - Saturday, October 11, 2014 - link
The biggest issue continues to be cost. While continuing to push bulk CMOS is more expensive in up-front cost, SOI has much higher fluid costs. There's also only one supplier of SOI wafers to my knowledge. (Soitec)Kidster3001 - Wednesday, October 29, 2014 - link
Modern chips are connected with a C4 process (Controlled Collapse Chip Connect) The interconnect side is down, the bulk side is up. The heatsink is touching the back of the wafer.nand - Friday, October 10, 2014 - link
when i was 18 and in college i couldn't get head my over this stuff - after few years of growing up it makes perfect sense...sammycbvb - Friday, October 10, 2014 - link
Awesome article. I was waiting for a simplified explanation of Semiconductors and you've delivered.GT69 - Friday, October 10, 2014 - link
Great article for this old EE whose career was mostly in sales and marketing, but who has had a great love for PC's since the days of Apple II and CP/M. Nice that someone has taken the time and effort to give this generalized explanation even if some of the nit-pickers quibble over a typo or some specific detail. Until one has had to actually produce such a piece he/she should refrain from too much criticism. Easy and quick it ain't! Kudos...Dr.Neale - Saturday, October 11, 2014 - link
After many years of editing scientific / technical / medical journal articles, I tend to see the structural details as well as the informational content.To me, a typo is like a dead pixel. If it can be removed, it makes the image or storyline that much more immersive and enjoyable to behold.
The purpose is aiding the author in polishing the article to perfection, not fault-finding or nit-picking.
Like many tech enthusiasts, an editor brings a passionate pursuit of excellence to his craft and to his team.
Like many other commenters here, I see myself as making a small contribution, from time to time, to the AnandTech team.
Dr.Neale - Saturday, October 11, 2014 - link
P.S. I have also authored or coauthored numerous articles (and a textbook chapter) in the fields of medical physics and medical imaging, including invited review articles.So I offer my appeciation and congratulations to Josh Ho for gifting us with an article of such surpassing excellence.
dew111 - Friday, October 10, 2014 - link
This was a good review of my semiconductor physics course. But with less math :)Arnulf - Friday, October 10, 2014 - link
Very nice technical article, unlike the usual consumerist Apple et al chaff that has swamped this site as of lately!Senti - Friday, October 10, 2014 - link
Exactly my thoughts! It's really sad to see how level of this site has dropped significantly over years due to caring for more mindless crowd; certain reviewers doesn't bother to actually understand what they are reviewing and just pushing for faster time to post and more numbers (that are by large part are quite unrelevant).But articles like this show that hope is not lost here – great job, would love to see more articles like this.
SanX - Friday, October 10, 2014 - link
This is what puzzling for a long time: the wavelength of ArF laser is 192nm, the feature size of Core M processor is 14nm or 14 times smaller. With NA=1 you can focus into spot of the Airy size equal approximately to wavelength only. Using phase shift trick you can probably drop that size twice to 96nm. Using nonlinearity of photoresist you can drop twice more or to 49nm. My guess is that using titlting of laser (i do not get how it actually works) they can get 24nm. Adding water you can get 24 / 1.33=18nm. How they get 14nm and sometimes even 10nm what Samsung claims with just the optical lithography?Kristian Vättö - Saturday, October 11, 2014 - link
Double (or more) patterning.EMM81 - Monday, October 13, 2014 - link
Over the past 20 years many tricks have been developed to overcome what was originally believed to be an optical limitation. Lithography tools are much more complicated than the brief descriptions given and have had many advances including going from aligners->steppers->scanners, NA=1.35, illumination system improvements, resist improvements, anti-reflective coating improvements, different types of phase shift on all reticles... On top of the fact that we can resolve sub 50nm pitches with 193nm light we use various double patterning schemes.abufrejoval - Saturday, October 11, 2014 - link
It's a wonderful article, something I'll quote and link to for a long time very much along the epochal piece Anand wrote on Flash.I'd like to see a followup or a mention to memristors, though. Not only because they are about to eliminate disk, flash, DRAM and SRAM, but because they also have such huge potential in FPGA and log redesign.
On top their stacking capabilities together with the low energy density and production cost may actually allow attenuating the need for process shrinks to the point where it almost feels as though Moore's law was continuing, but not through process shrinks.
abufrejoval - Saturday, October 11, 2014 - link
need edit!last two words on 2nd paragraph should read "logic redesign".
stimudent - Saturday, October 11, 2014 - link
You won't find an article like this on childish websites like Tech Report.l_d_allan - Saturday, October 11, 2014 - link
I don't find this an "Intro", but rather like a summary of EE 301 for people who have taken EE 101, EE 201, and EE 301. To me, it assumes a high level to prerequisites.Also, the article could benefit by more care taken to definitions ... for example, EUV is used repeatedly on the fourth page, but not defined until the sixth page.
The0ne - Saturday, October 11, 2014 - link
"But there is far more to be done, as literally everything we write about at AnandTech depends upon ever faster, smaller, and more efficient transistors packed as tightly as possible. Without this continued innovation, the PC, smartphone, and wearables that we see today would be impossible to make."Thank you. Needed this article to remove the foul taste left my the recent iPhone reviews reasoning the phone is great because it can't improve any more.
Doomtomb - Monday, October 13, 2014 - link
Awesome article. Great introduction to people curious about the industry. Some terms were glossed over that might help explain semiconductor physics more such as work function and crystal lattice, but there's only so much you can cover at oncevermaasit - Monday, October 13, 2014 - link
This was awesome article. Keep goingDIYEyal - Monday, October 13, 2014 - link
One of the best articles on this site. Good job!toyotabedzrock - Tuesday, October 14, 2014 - link
It sounds like electron beam is the best path forward but I have a feeling the bean counters will push for using the nano method because it would create "efficiencies" that shareholders would love. I don't see any mold at that feature size being reusable. It seems like we are approaching a size where we will be lowering energy efficiency due to leakage and limitations it clock speed.I remember reading about a new type of transistor Intel was working on that required much less voltage, that would be a good next step.
Kidster3001 - Wednesday, October 29, 2014 - link
That would be NTV or Near Threshold Voltage. Basically, requires a lot less energy to turn transistors On and Off, which just happens to be the only time they consume energy (not counting leakage)victorson - Tuesday, October 14, 2014 - link
Great work, Joshua, I still find it a bit too challenging of a read, especially at the chemistry level, but will definitely chew through this in a couple of attempts.Marvin Wankerstein - Sunday, October 19, 2014 - link
First - very nice article. It was nice to read such a good summary of much of my graduate school days.I was rather disappointed that you did touch on what a stepper is and what the term "stepping" means since I see it so frequently misused.
Regardless, I enjoyed the article very much.
LapX - Tuesday, October 28, 2014 - link
I want to major in electrical engineering (Ihave 7 years to go before I'm finished) and I find this article very interesting but I still can't figure out how you can create logic with the transistors or how do they switch from on to off, is it switching itself when the current is too low/high if I undestood correctly?campbbri - Wednesday, October 29, 2014 - link
Thank you for the great article!SanX - Sunday, May 24, 2015 - link
OK, take 50nm, with doublepatterning 25. How they get 14 and even 10nm? That needs something else. You can not make 10nm line with 20x longer wavelength