PCI-SIG has released version 0.5 of the PCIe 6.0 specification to its members this week. The new, "first draft" version of the spec includes the feedback the group got from its members after publication of version 0.3 back in October. With their latest update, PCI-SIG remains confident that it is on track to finalize the PCIe 6.0 standard in 2021.

It took PCI-SIG long seven years to complete the PCIe 4.0 specification, a long slog that the group has committed to avoiding going forward for PCIe 5.0 and beyond. With PCIe 6.0, PCI-SIG is keeping up that rapid pace of development, releasing the first draft version of the spec less than a year after formal announcement of the spec.

Overall, PCI-SIG has five key steps in creating a PCIe specification:

  • Version 0.3 is beheld as a Concept and outlines the key features and architecture of the technology. In case of PCIe 6.0, we are talking about 64 GT/s per lane speed, pulse amplitude modulation with 4 levels (PAM-4) encoding, and forward error correction (FEC).
  • Version 0.5 is considered as the First Draft specification and so it covers all the key aspects of the architecture and includes feedback from interested parties (within PCI-SIG) to version 0.3. Members of the group will be able to add new functionality to the technology at this point.
  • Version 0.7 is deemed to be the Complete Draft, everything has to be defined at all levels and electrical specifications must have been validated via test chips. No new features may be added after release of this iteration of the specification.
  • Version 0.9 is the Final Draft that is meant to allow PCI-SIG members to review the technology for their intellectual property.
  • Version 1.0 is the Final Release.

The publication of version 0.5 of the PCIe 6.0 specification is essentially the final call for submissions of the new features by PCI-SIG member companies. Furthermore, with the first draft available, companies can start designing test silicon to ensure that everything works and even begin preliminary work on commercial chips.

The next milestone for the PCIe 6.0 specification will be the upcoming PCI-SIG Developers Conference 2020 in early June, where the group plans to present deep dives into the features of the technology.

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Source: PCI-SIG

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  • mode_13h - Friday, February 21, 2020 - link

    I mean AT LEAST a dual-CPU configuration, if you use their mainstream 2-socket servers. In the single-CPU config, none of the x16 slots will be connected to socket 0.
  • schujj07 - Friday, February 21, 2020 - link

    The chart shows the wrong GB/s for bandwidth. Each version of PCIe is off by 1 generation. PCIe 1.0 is 4GB/s (x16) not 8GB (x16), 2.0 8GB/s (x16) not 16GB (x16), etc...
  • sheh - Friday, February 21, 2020 - link

    I guess they mean the full-duplex rate.
  • mode_13h - Friday, February 21, 2020 - link

    True, but the chart should make it clear. For things like graphics, data flows are not symmetric.
  • shabby - Friday, February 21, 2020 - link

    Is it safe to say that long delay between pcie 3 and 4 was because of intel not developing any new platforms and amd still sleeping?
  • mode_13h - Friday, February 21, 2020 - link

    I'd say lack of demand. Until NVMe SSDs and deployment of 100 Gigabit network really heated up, PCIe 3.0 was pretty adequate.
  • mode_13h - Friday, February 21, 2020 - link

    AI, as well.
  • Qasar - Saturday, February 22, 2020 - link

    well, intel did say mainstream doesnt need more then 4 cores......
  • Brane2 - Friday, February 21, 2020 - link

    Where does copper connect end ?
    I thought that 32G/s/pair was already over practical limit for copper pair and any practical reach.
    And even that was done on FPGAs of astronomical price and with few transceivers.

    So PCIe switched to QAM and is going for even finer mopdulations.

    ISn't this practically raping the initial PCIe concepts ?
    Hasn't the time long came for somebody to come with photonic Rx/Tx macro for new geometries ?
  • techguymaxc - Friday, February 21, 2020 - link

    PCI SIG really screwed the pooch after the ratification of the 3.0 standard

    We've had products featuring PCI-e 3.0 since 2011. It's 2020 and you can only get 4.0 on a few AMD motherboard (zero Intel) and not only is 5.0 here, but 6.0 next year? Please.

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