AMD Zen Architecture Roadmap: Zen 5 in 2024 With All-New Microarchitectureby Ryan Smith on June 9, 2022 4:21 PM EST
Today is AMD’s Financial Analyst Day, the company’s semi-annual, analyst-focused gathering. While the primary purpose of the event is for AMD to reach out to investors, analysts, and others to demonstrate the performance of the company and why they should continue to invest in the company, FAD has also become AMD’s de-facto product roadmap event. After all, how can you wisely invest in AMD if you don’t know what’s coming next?
As a result, the half-day series of presentations is full of small nuggets of information about products and plans across the company. Everything here is high-level – don’t expect AMD to hand out the Zen 4 transistor floorplan – but it’s easily our best look at AMD’s product plans for the next couple of years.
Kicking off FAD 2022 with what’s always AMD’s most interesting update is the Zen architecture roadmap. The cornerstone of AMD’s recovery and resurgence into a competitive and capable player in the x86 processor space, the Zen architecture is the basis of everything from AMD’s smallest embedded CPUs to their largest enterprise chips. So what’s coming down the pipe over the next couple of years is a very big deal for AMD, and the industry as a whole.
Zen 4: Improving Performance and Perf-Per-Watt, Shipping Later This Year
Diving right in, AMD is currently in the process of ramping up their Zen 4 architecture-based products. This includes the Ryzen 7000 (Raphael) client CPUs, as well as their 4th generation EPYC (Genoa) server CPUs. Both of these are due to launch later this year.
We’ve seen bits and pieces of information on Zen 4 thus far, most recently with the Ryzen 7000 announcement at Computex. Zen 4 brings new CPU core chiplets as well as a new I/O die, adding support for features such as PCI-Express 5.0 and DDR5 memory. And on the performance front, AMD is aiming for significant performance-per-watt and clockspeed improvements over their current Zen 3-based products.
Meanwhile, AMD is following up that Computex announcement by clarifying a few things. In particular, the company is addressing questions around Instruction per Clock (IPC) expectations, stating that they expect Zen 4 to offer an 8-10% IPC uplift over Zen 3. The initial Computex announcement and demo seemed to imply that most of AMD’s performance gains were from clockspeed improvements, so AMD is working to respond to that without showing too much of their hand months out from the product launches.
Coupled with that, AMD is also disclosing that they’re expecting an overall single-threaded performance gain of greater than 15% – with an emphasis on “greater than.” ST performance is a mix of IPC and clockspeeds, so at this point AMD can’t get overly specific since they haven’t locked down final clockspeeds. But as we’ve seen with their Computex demos, for lightly threaded workloads, 5.5GHz (or more) is currently on the table for Zen 4.
Finally, AMD is also confirming that there are ISA extensions for AI and AVX-512 coming for Zen 4. At this point the company isn’t clarifying whether either (or both) of those extensions will be in all Zen 4 products or just a subset – AVX-512 is a bit of a space and power hog, for example – but at a minimum, it’s reasonable to expect these to show up in Zen 4 server parts. The addition of AI instructions will help AMD keep up with Intel and other competitors in the short run, as CPU AI performance has already become a battleground for chipmakers. Though just what this does for AMD’s competitiveness there will depend in large part on just what instructions (and data types) get added.
AMD will be producing three flavors of Zen 4 products. This includes the vanilla Zen 4 core, as well as the previously-announced Zen 4c core – a compact core that is for high density servers and will be going into the 128 core EPYC Bergamo processor. AMD is also confirming for the first time that there will be V-Cache equipped Zen 4 parts as well – which although new information, does not come as a surprise given the success of AMD’s V-Cache consumer and server parts.
Interestingly, AMD is planning on using both 5nm and 4nm processes for the Zen 4 family. We already know that Ryzen 7000 and Genoa are slated to use one of TSMC’s 5nm processes, and that Zen 4c chiplets are set to be built on the HPC version of N5. So it’s not immediately clear where 4nm fits into AMD’s roadmap, though we can’t rule out that AMD is playing a bit fast and loose with terminology here, since TSMC’s 4nm processes are an offshoot of 5nm (rather than a wholly new node) and are typically classified as 5nm variants to start with.
At this point, AMD is expecting to see a >25% increase in performance-per-watt with Zen 4 over Zen 3 (based on desktop 16C chips running CineBench). Meanwhile the overall performance improvement stands at >35%, no doubt taking advantage of both the greater performance of the architecture per-thread, and AMD’s previously disclosed higher TDPs (which are especially handy for uncorking more performance in MT workloads). And yes, these are terrible graphs.
Zen 5 Architecture: All-New Microarchitecture for 2024
Meanwhile, carrying AMD’s Zen architecture roadmap into 2024 is the Zen 5 architecture, which is being announced today. Given that AMD isn’t yet shipping Zen 4, their details on Zen 5 are understandably at a very high level. None the less, they also indicate that AMD won’t be resting on their laurels, and have some aggressive updates planned.
The big news here is that AMD is terming the Zen 5 architecture as an “All-new microarchitecture”. Which is to say, it’s not merely going to be an incremental improvement over Zen 4.
In practice, no major vendor designs a CPU architecture completely from scratch – there’s always going to be something good enough for reuse – but the message from AMD is clear: they’re going to be doing some significant reworking of their core CPU architecture in order to further improve their performance as well as energy efficiency.
As for what AMD will disclose for right now, Zen 5 will be re-pipelining the front end and once again increasing their issue width. The devil is in the details here, but coming from Zen 3 and its 4 instruction/cycle decode rate, it’s easy to see why AMD would want to focus on that next – especially when on the backend, the integer units already have a 10-wide issue width.
Meanwhile, on top of Zen 4’s new AI instructions, Zen 5 is integrating further AI and machine learning optimizations. AMD isn’t saying much else here, but they have a significant library of tools to pick from, covering everything from AI-focused instructions to adding support for even more data types.
AMD expects the Zen 5 chip stack to be similar to Zen 4 – which is to say that they’re going to have the same trio of designs: a vanilla Zen 5 core, a compact core (Zen 5c), and a V-Cache enabled core. For AMD’s customers this kind of continuity is very important, as it gives customers a guarantee that AMD’s more bespoke configurations (Zen 4c & V-Cache) will have successors in the 2024+ timeframe. From a technical perspective none of this is too surprising, but from a business standpoint, customers want to make sure they aren’t adopting dead-end hardware.
Finally, AMD has an interesting manufacturing mix planned for Zen 5. Zen 5 CPU cores will be fabbed on a mix of 4nm and 3nm processes, which unlike the 5nm/4nm mix for Zen 4, TSMC’s 4nm and 3nm nodes are very different. 4nm is an optimized version of 5nm, whereas 3nm is a whole new node. So if AMD’s manufacturing plans move ahead as currently laid out, Zen 5 will be straddling a major node jump. That said, it’s not unreasonable to suspect that AMD is hedging their bets here and leaving 4nm on the table in case 3nm isn’t as far along as they’d like.
Wrapping things up, the Zen 5 architecture is slated for 2024. AMD isn’t giving any further information on when in the year that might be, though looking at Zen 3 and Zen 4, both of those were/will be released later on in 2020 and 2022 respectively. So H2/EOY 2024 is as good as guess as any.
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Kangal - Friday, June 10, 2022 - linkPlenty of morons around. I found the posts, and realised it was on another site. But you are right about the farts.
Khanan - Friday, June 10, 2022 - linkZen 4 isn’t a refresh of Zen 3. Higher IPC different ram controller, way higher clocks, different instructions. Either you didn’t read the article or don’t understand much about CPUs in general.
mode_13h - Saturday, June 11, 2022 - link> I said Zen4 was a refresh of Zen3 on the new platform
It's clearly more than a simple port of Zen3 to 5 nm. We already saw how little benefit the Ryzen 6000's gain from the 6 nm port, and if you go back to Zen+ (i.e. 2000-series non-APUs), you'll see that 12 nm also offered only a couple %.
So, whatever they did, it might not be a roots-and-branches overhaul, but it's also a lot more than a straight port + some AI instructions.
GeoffreyA - Saturday, June 11, 2022 - linkLikely, the usual widening of the retire queue, more scheduler entries, improved branch prediction, and bigger micro-op cache.
GeoffreyA - Saturday, June 11, 2022 - link+ bigger register files, etc.
Shorty_ - Saturday, June 11, 2022 - linkI don't get why you're all so upset, they spelt this out as their plan in 2019:
He also indicated that AMD's server CPU launches are set to rely on the "tick-tock" cadence that was once the hallmark of Intel CPU launches, with the launch of a CPU platform that relies on a new manufacturing process node but the same microarchitecture as the last platform (the "tick") followed by a platform that relies on a new microarchitecture but the same manufacturing process node (the "tock").
michael2k - Thursday, June 9, 2022 - linkI was hoping to see a BIG.little design from them.
Dolda2000 - Thursday, June 9, 2022 - linkI don't think they need it, at least not yet. There was an article at Chips & Cheese that elucidated how Zen 2 (yes 2, not 3!) was extremely competitive in total energy use with Gracemont, and that Zen 2 on mobile blew completely past Gracemont on every power level.
qwerty109 - Friday, June 10, 2022 - linkIt is little understood reality (and intentionally obfuscated by Intel) that E cores (Atoms) are not actually energy efficient - they're actually worse or similar to big P-cores. However, they're a lot smaller - they are die space Efficient.
The whole BIG.little on x86 is not there for energy efficiency like on ARM/mobile but exist so Intel can win on Cinebench and heavily multi-threaded workloads because P-cores can't compete with Zen otherwise. They can't compete because they've grown the P-core to ridiculous size in the hunt for IPC, and there was no way to back out of that (and losing process advantage to TSMC didn't help).
schujj07 - Friday, June 10, 2022 - linkIntel needs the BIG.little to help reign in their power consumption. Their P cores when running all out on AVX workloads suck a lot of power. The 12900K with 8P+8E cores sucks down 272W in 16c/24t configuration and 239W in 8c/16t mode. The E cores are using about 4W/core but the P cores are using ~30W/core. If Intel wanted to do a 10P core chip it would be breaking 300W under full AVX. The Core uArch hasn't been really that power efficient since Broadwell. It wasn't designed to go over 4c/8t at first and over 4.0GHz its power curve looks bad. However, due to pressure from Zen, which was designed around efficiency and 8c/16t, Intel had to push Core to the limits.