New Technology Features for 2024: RibbonFETs

One of the major features of this roadmap is highlighted when it shifts to 20A, Intel’s process name referring to Angstroms rather than nanometers. At this juncture, as mentioned above, Intel will be transitioning from its FinFET design over to a new type of transistor, known as a Gate-All-Around transistor, or GAAFET. In Intel’s case, the marketing name they are giving their version is RibbonFET.

It has been widely expected that once the standard FinFET runs out of steam that the semiconductor manufacturing industry will pivot to GAAFET designs. Each of the leading edge vendors call their implementation something different (RibbonFET, MBCFET), but it is all using the same basic principle – a flexible width transistor with a number of layers helping drive transistor current. Where FinFETs relies on multiple quantized fins for source/drain and a cell height of multiple tracks of fins, GAAFETs enable a single fin of variable length, allowing the current for each individual cell device to be optimized in power, performance, or area.

Image from Samsung

Intel has been discussing GAAFETs in technical semiconductor conferences for a number of years, at the International VLSI conference in June 2020, then CTO Dr. Mike Mayberry showcased a diagram with the enhanced electrostatics of moving to a GAA design. At the time we asked about Intel’s timescale for implementing GAA in volume, and were told to expect them ‘within 5 years’. At present Intel’s RibbonFET is due to come with the 20A process, likely to be productized by the end of 2024 based on the roadmaps outlined above.

In Intel’s RibbonFET diagrams for this event, they’re showing both PMOS and NMOS devices, as well as what clearly looks like a 4-stack design. Given that I have seen presentations from Intel involving anything from 2-stack to 5-stack at the industry conferences, we confirmed that Intel will indeed be using a 4-stack implementation. The more stacks that are added, the more process node steps are required for manufacturing, and to quote Intel’s Dr. Kelleher, ‘it’s easier to remove a stack than to add one!’. Exactly what is the right number of stacks for any given process or function is still an active area of research, however Intel seems keen on four.

In comparison with Intel’s competitors,

TSMC is expected to transition to GAAFET designs on its 2nm process. At its annual Tech Symposium in August 2020, TSMC confirmed that it would remain on FinFET technology all the way to its 3nm (or N3) process node as it has been able to find significant updates to the technology to allow performance and leakage scaling beyond what was initially expected – N3 is quoted to have up to a 50% performance gain, 30% power reduction, or 1.7x density gain over TSMC N5. Staying on FinFETs, TSMC stated, provides comfort to its customers. Details on TSMC’s N2 have not been disclosed.

Samsung by contrast has stated that it will be introducing its GAA technology with its 3nm process node. Back in Q2 2019, Samsung Foundry announced the first v0.1 development kit of its new 3GAE process node using GAAFETs was being made available to key customers. At the time Samsung predicted volume production by end of 2021, and the latest announcement suggests that while 3GAE will deploy in 2022 internally, main customers may have to wait until 2023 for its more advanced 3GAP process.

To put this into a table:

Gate-All-Around Transistor Deployment
AnandTech Name Process Timeframe
Intel RibbonFET 20A 2024
18A 2025
TSMC GAAFET N2 / 2nm EoY 2023?
Samsung MBCFET 3GAE 2022
3GAP 2023

By this metric, Samsung might be first to the gate, albeit with an internal node, while TSMC is going to get a lot out of its N5, N4, and N3 nodes first. Around end of year 2023 is when it gets interesting as TSMC may be looking at its N2 designs, while Intel is committed to that 2024 timeframe. The official slide says first half 2024, though as a technology announcement vs product announcement, there is often some lag between the two.


New Technology Features for 2024: PowerVias

The other arm of Intel’s 20A designs in 2024 is what the company is calling ‘PowerVia’. The concept here pivots the traditional understanding of chip design from a multi-layered cake into a sandwich of sorts.

The manufacturing process of a modern circuit starts the transistor layer, M0, as the smallest layer. Above that, additional metal layers are added at increasing sizes to account for all the wiring needed between the transistors and different parts of the processor (cache, buffers, accelerators). A modern high-performance processor typically has anywhere from 10 to 20 metal layers in its design, with the top layer where the external connections are placed. The chip is then flipped over (known as flip chip) so that the chip can talk to the outside world with those connections on the bottom, and the transistors at the top.

With PowerVias, we now put the transistors in the middle of the design. On one side of the transistors we put the communication wires that allow parts of the chip to talk to each other. On the other side are all the power related connections (along with power gating control). In essence, we moved to a sandwich where the transistors are the filling. This is usually referred to as ‘backside power delivery’ in the industry – PowerVia is Intel’s marketing name.

From a holistic level, we can ascertain that the benefits of this design start with simplifying both the power and the connectivity wires. Typically these have to be designed to ensure there is no signaling interference, and one of the big sources of interference are large power carrying wires, so this takes them out of the equation by putting them on the other side of the chip. It also works the other way – the interference of the interconnected data wires can increase the power delivery resistance, resulting in lost energy and thermals. In this way, PowerVias can help new generations of transistors as drive currents increase by having the power directly there, rather than routed around the connectivity.

There are a couple of hurdles here to mention however. Normally we start manufacturing the transistors first because they are the most difficult and most likely to have defects – if a defect is caught early in the metrology (defect detection in manufacturing), then that can be reported as early in the cycle as possible. By having the transistors in the middle, Intel would now be manufacturing several layers of power first before getting to the tough bit. Now technically these layers of power would be super easy compared to the transistors, and nothing is likely to go wrong, but it is something to consider.

The second hurdle to think about is power management and thermal conductivity. Modern chips are built transistor first into a dozen layers ending with power and connections, and then the chip is flipped, so the power hungry transistors are now at the top of the chip and the thermals can be managed. In a sandwich design, that thermal energy is going to go through whatever ends up on the top of the chip, which is most likely going to be the internal communication wires. Assuming that the thermal increase of these wires doesn’t cause any issues in production or regular use, then perhaps this isn’t so much of an issue, however it is something to consider when heat has to be conducted away from the transistors.

It is worth noting that this ‘backside power delivery’ technology has been in development for a number of years. Across five research papers presented at the VLSI symposium in 2021, imec presented several papers on the technology showing recent advancements when using FinFETs, and in 2019 Arm and imec announced similar technology on an Arm Cortex-A53 built on an equivalent 3nm process in imec’s research facilities. Overall the technology reduces the IR drop on the design, which is becoming increasingly harder to achieve on more advanced process node technologies to drive performance. It will be interesting to see the technology when it is in high volume on high performance processors.

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  • mode_13h - Thursday, July 29, 2021 - link

    Good journalism requires impartiality, which is hard to maintain when you're directly involving yourself in the agenda of those you're reporting on.

    Impartiality isn't about not having opinions. It's about separating them from one's reporting.
  • Oxford Guy - Thursday, July 29, 2021 - link

    Impartiality is a myth.

    Everyone brings many biases, regardless of what label they stick on themselves. It's better to be open about those biases than to feign objectivity.

    Come clean with one's biases (as much as one can, since they are a form of blindness) and, simultaneously, try to present the facts — clearly/thoroughly.

    Your vision of a journalist sounds like a stenographer. Journalism is supposed to have activism as part of its function. That's what makes it different from stenography.
  • mode_13h - Sunday, August 1, 2021 - link

    > Impartiality is a myth.

    How lame. Just because there's no such thing as a perfectly neutral reporter doesn't mean that journalistic standards don't still have value.

    > It's better to be open about those biases than to feign objectivity.

    This is a canard used to legitimize partisan media. Time and again, surveys of consumers of partisan media have been shown to be less well-informed about relevant subject material.

    > Come clean with one's biases

    Yes, conflict of interests should be disclosed. However, one should take reasonable measures not to *further* said entanglements. That makes objectivity even more difficult.

    > Your vision of a journalist sounds like a stenographer.

    No, and I already explained the difference.

    > Journalism is supposed to have activism as part of its function.

    No, but thanks for at least confirming your ignorance on the subject.

    Activism should be reserved for editorials. There should be a bright line between reporting and editorial content.

    > That's what makes it different from stenography.

    No. Where it differs is by providing context and fact-checking.
  • Spunjji - Friday, July 30, 2021 - link

    @mode_13h - I guess I just disagree with you that Ian has "involved [him]self in the agenda" of Intel by advocating for some sort of change in their process naming conventions. It's equally likely he was tired of having to write articles explaining the difference between foundry Xnm and Intel XXnm, and/or the difference between "++", "+++" and "ESF".
  • GeoffreyA - Friday, July 30, 2021 - link

    I've got to agree with Ian's trying to shake some sense into Intel.
  • GeoffreyA - Saturday, July 31, 2021 - link

    I think both points of view are right (mode_13h's and Oxford Guy's) and need to be combined.
  • mode_13h - Sunday, August 1, 2021 - link

    > both points of view are right ... and need to be combined.

    Um, how?
  • GeoffreyA - Sunday, August 1, 2021 - link

    While perfect impartiality is hard to find, it does exist as an ideal which we've got to keep before us. Without that gold standard, practice would sink lower and lower.
  • mode_13h - Sunday, August 1, 2021 - link

    > I just disagree with you that Ian has "involved [him]self in the agenda"
    > of Intel by advocating for some sort of change in their process naming conventions.

    What it does is give him a sense of ownership of their new process naming scheme, and that risks coloring his reporting. I'm not going to reread the entire article just to find examples, but I did note a few instances of what seemed to be favorable coverage. I can't say that's the result of his advocacy, but I wouldn't even have the question if he hadn't committed it.

    > It's equally likely he was tired of having to write articles explaining the difference
    > between foundry Xnm and Intel XXnm, and/or the difference between "++", "+++"
    > and "ESF".

    First, that's not a good excuse for advocacy. Reporters always face the issue of having to provide context for readers who haven't been following the subject closely. The magic of hyperlinks can be used to minimize the amount of repetition, by simply writing an explainer and linking to it from articles that deal with the relative differences between process nodes.

    Second, he's still going to be in a similar position of potentially having to explain the differences between a given TSMC node and whichever Intel node is relevant. So, I don't see how this really improves the situation.
  • Oxford Guy - Wednesday, August 11, 2021 - link

    Slapping the word ‘editorial’ onto a piece of writing doesn’t magically change it.

    All it does is typically label the piece an example of casual sloppy thinking.

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