Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!by Dr. Ian Cutress on July 26, 2021 5:00 PM EST
Sidebar on Intel EUV
In all of these announcements, one thing to highlight is Intel mentioning its relationship with ASML, the sole company that manufactures the EUV machines powering production of leading edge semiconductor manufacturing.
ASML is a unique company in that it is the only one that can produce these machines, because the technology behind them is often tied up with its partners and research, but also because all the major silicon manufacturers are heavily invested in ASML. For any other company to compete against ASML would require building a separate network of expertise, a decade of innovation and design, and a lot of capital. None of the major silicon vendors want to disturb this balance and go off on their own, lest it shuts them out of the latest manufacturing technology, and no research fund sees competing against the embedded norm as a viable opportunity. This means that anyone wanting EUV specialist technology has to go to ASML.
In 2012, it was reported that Intel, Samsung, and TSMC all invested in ASML. This was, at the time, to jumpstart EUV development along with migrating from 300mm wafers to 450mm wafers. While we haven’t moved to 450mm wafers yet (and there are doubts we will any time in the next decade), EUV is now here. Intel’s 2012 investment of $2.1 billion gave them a 10% stake in ASML, with Intel stating that it would continue investing up to a 25% stack. Those stakes are now below the 5% reporting threshold, but all three of the major foundry customers are still big owners, especially as ASML’s market cap has risen from $24 Billion in 2012 to $268 Billion in 2021 (surpassing Intel).
As major investors but also ASML’s customers, the race has been on for these foundries to acquire enough EUV machines to meet demand. TSMC reported in August 2020 that it has 50% of all EUV machines manufactured at ASML for its leading edge processes. Intel is a little behind, especially as none of Intel’s products in the market yet use any EUV. EUV will only intercept Intel’s portfolio with its new Intel 4 process, where it will be used extensively, mostly on the BEOL. But Intel still has to order machines when they need them, especially as there are reports that ASML currently has backorders of 50 EUV machines. In 2021, ASML is expected to manufacture around 45-50 machines, and 50-60 in 2022. The exact number of machines Intel has right now, or has ordered from ASML, is unknown. It is expected that each one has a ~$150m price tag, and can take 4-6 months to install.
With all that being said, Intel’s discussion point today is that it will be the lead customer for ASML’s next generation EUV technology known as High-NA EUV. NA in this context relates to the ‘numerical aperture’ of the EUV machine, or to put simply, how wide you can make the EUV beam inside the machine before it hits the wafer. The wider the beam before you hit the wafer, the more intense it can be when it hits the wafer, which increases how accurately the lines are printed. Normally in lithography to get better printed lines, we move from single patterning to double patterning (or quad patterning) to get that effect, which decreases yield. The move to High-NA would mean that the ecosystem can stay on single patterning for longer, which some have quoted as allowing the industry to ‘stay aligned with Moore’s Law longer’.
|ASML's EUV Shipments|
|Target (Total)||-||-||-||20 (18)||30 (26)||35 (33)||45-50|
|2018 and beyond is split per quarter for actual shipped numbers
Data taken from ASML's Financial Reports
Current EUV systems are NA 0.33, while the new systems are NA 0.55. ASML’s latest update suggests that it expects customers to be using High-NA for production in 2025/2026, which means that Intel is likely going to be getting the first machine (ASML NXE:5000 we think) in mid-2024. Exactly how many High-NA machines ASML intends to produce in that time frame is unknown, as if they flood the market, having the first won’t be a big win. However if there is a slow High-NA ramp, it will be up to Intel to capitalize on its advantage.
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shabby - Monday, July 26, 2021 - linkLol this guy is a great comedian 😂
at_clucks - Tuesday, July 27, 2021 - linkThey're also preparing the elusive 0nm process. Really tiny, great power consumption too.
RealBeast - Tuesday, July 27, 2021 - linkDon't get sucked into those 0nm chips, wait for the negative nm the following year. ;)
linuxgeex - Wednesday, July 28, 2021 - linkIntel's minds have come up with a new complex plane process. They measure their feature size by taking the square root of the height of the gate. By extending the gate downward, their measurements start at -1, leading to measurements in the scale of i, which tickles their marketing department no end. Sadly, i doesn't deliver on a real timeline.
mode_13h - Thursday, July 29, 2021 - link:D
Santoval - Sunday, October 24, 2021 - linkDo not disregard complex timelines so casually. Intel can well deliver in a + bi, where a = Q (quarter), b = year and i is, you know, the imaginary thingy.
Assuming a claimed Q1 2025 delivery in the real plane of Intel's RibbonFET 20A parts, in the complex plane where Intel lives the actual delivery would be in Q1 + 2025i.
Let's say Jan 2025i; right after the complex holiday season of 2024 / 2025, complete with an imaginary Santa and complex elves.
nandnandnand - Monday, July 26, 2021 - link"Isn't Intel Just Trying To Pull The Wool Over Our Eyes?"
Yes. Otherwise there's no need for the marketing dept to magically shrink the fake 10nm node to become a fake 7nm.
ianmills - Monday, July 26, 2021 - linkWhen everyone lies nobody is wrong...
nandnandnand - Monday, July 26, 2021 - linkAs long as they put out accurate transistors per square millimeter estimates, everything's fine.
Who is the biggest liar now? Probably Samsung.
DigitalFreak - Monday, July 26, 2021 - linkNope. Still Intel.