At TSMC’s annual Technology Symposium, the Taiwanese semiconductor manufacturer detailed characteristics of its future 3nm process node as well as laying out a roadmap for 5nm successors in the form of N5P and N4 process nodes.

Starting off with TSMC’s upcoming N5 process node which represents its 2nd generation deep-ultraviolet (DUV) and extreme-ultraviolet (EUV) process node after the rarely used N7+ node (Used by the Kirin 990 SoC for example). TSMC has been in mass production for several months now as we’re expecting silicon shipping to customers at this moment with consumer products shipping this year – Apple’s next-generation SoCs being the likely first candidates for the node.

TSMC details that N5 currently is progressing with defect densities one quarter ahead of N7, with the new node having better yields at the time of mass production than both their predecessor major nodes N7 and N10, with a projected defect density that’s supposed to continue to improve past the historic trends of the last two generations.

The foundry is preparing a new N5P node that’s based on the current N5 process that extends its performance and power efficiency with a 5% speed gain and a 10% power reduction.

Beyond N5P, TSMC is also introducing the N4 node that represents a further evolution from the N5 process, employing further EUV layers to reduce masks, with minimal migration work required by chip designers. We’ll be seeing N4 risk production start in 4Q21 for volume production later in 2022.

Today’s biggest news was TSMC’s disclosure on their next big leap past the N5 process node generation family, which is the 3nm N3 node. We’ve heard that TSMC had been working on defining the node back last year with progress going well.

Contrary to Samsung’s 3nm process node which makes use of GAA (Gate-all-around) transistor structures, TSMC will instead be sticking with FinFET transistors and relying on “innovative features” to enable them to achieve the full-node scaling that N3 promises to bring.

Advertised PPA Improvements of New Process Technologies
Data announced during conference calls, events, press briefings and press releases
Power -60% <-40% -10% -15% -30% -10% -25-30%
Performance +30% ? +7% +10% +15% +5% +10-15%
Logic Area

Reduction %













Q2 2019
Q2 2020 2021 H2 2022

Compared to it’s N5 node, N3 promises to improve performance by 10-15% at the same power levels, or reduce power by 25-30% at the same transistor speeds. Furthermore, TSMC promises a logic area density improvement of 1.7x, meaning that we’ll see a 0.58x scaling factor between N5 and N3 logic. This aggressive shrink doesn’t directly translate to all structures, as SRAM density is disclosed at only getting a 20% improvement which would mean a 0.8x scaling factor, and analog structures scaling even worse at 1.1x the density.

Modern chip designs are very SRAM-heavy with a rule-of-thumb ratio of 70/30 SRAM to logic ratio, so on a chip level the expected die shrink would only be ~26% or less.

N3 is planned to enter risk production in 2021 and enter volume production in 2H22. TSMC’s disclosed process characteristics on N3 would track closely with Samsung’s disclosures on 3GAE in terms of power and performance, but would lead more considerably in terms of density.

We’ll be posting more detailed content from TSMC’s Technology Symposium in due course, so please stay tuned for more information and updates.

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  • psychobriggsy - Tuesday, August 25, 2020 - link

    TSMC's generations are "what can we achieve to hit a 2 year cadence reliably". For 5nm that was 1.8x density. For 3nm it is 1.7x density. 2nm might be 1.6x density. 1.4nm might be 1.5x density.

    What matters for TSMC and their customers is that every 2 years there is a measurable improvement in the process. Other technology can pick up the slack - chiplets, poorly scaling logic on older process dies, and so on.

    Intel went berzerk with their 2.7x density target, and it's cost them 4 years (from 2 years ahead to 2 years behind). They don't talk about what the real world scaling of their working 10nm is now, but it isn't 2.7x looking at the achieved transistor densities of Lakefield, ICL, TGL.
  • Spunjji - Wednesday, August 26, 2020 - link

    Solid summary.

    Gondalf and the other Intel shills are still operating on that 2.7X figure. Apparently because Intel refuse to talk about density now, that means we can't infer that they haven't achieved it... or something.
  • Spunjji - Wednesday, August 26, 2020 - link

    Lack of SRAM scaling will affect GPU makers the least, surely? They're more constrained by how densely you can pack the ALUs.

    I will never tire of observing the different ways in which you manage to be wrong.
  • shabby - Monday, August 24, 2020 - link

    Intel: hey tsmc slow down, please!
  • Spunjji - Wednesday, August 26, 2020 - link

    I have a rock in my shoe! 😂
  • s.yu - Monday, August 24, 2020 - link

    N7P vs N7 and N7+ vs N7 read exactly the same in the chart, I presume that's wrong?
  • brucethemoose - Monday, August 24, 2020 - link

    What about eDRAM, the stuff that IBM seems to like so much?

    If last level SRAM cache is going to take up so much space on N3, shrinking it down by replacing it with eDRAM may be worth the performance hit.
  • Kevin G - Tuesday, August 25, 2020 - link

    IBM hasn't indicated either way that their POWER10 will be using eDRAM but it looks like they've moved back to SRAM. It is interesting that the L3 cache capacity hasn't changed much as the POWER9 had 120 MB where as POWER10 shifts to 128 MB. Of note is that slice of L3 per core has moved from 15 MB down to 8 MB due to the changing number of cores and layout organization. Shifting back to SRAM is likely why IBM hasn't radically increased core counts vs. POWER9. Die size is ~90 mm^2 smaller than the previous generation though.
  • eek2121 - Monday, August 24, 2020 - link

    TSMC is on fire!
  • albertmamama - Monday, August 24, 2020 - link

    Looks like Intel@22nm, a full node award all other players.

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