AMD Updated EPYC Roadmap: 5th Gen EPYC "Turin" Announced, Coming by End of 2024
by Gavin Bonshor on June 9, 2022 5:00 PM EST
As part of AMD's Financial Analysts Day 2022, AMD has provided updates to its Server CPU roadmap going into 2024. The biggest announcement is that AMD is already planning for the (next) next-gen core for its successful EPYC family, the 5th generation EPYC series, which has been assigned the codenamed Turin. Some key announcements include various segmentations of its expected EPYC 7004 portfolio, including Genoa, Bergamo, Genoa-X, and Siena.
From the launch of AMD's EPYC 2nd generation products Codenamed Rome back in August 2019, the release of the updated EPYC 7003 processors, including both Milan and Milan-X, the next generation of EPYC 7004 codenamed Genoa is expected to launch in Q4 2022. Genoa will feature up to 96 Zen 4 cores based on TSMC's 5 nm process node, with the new SP5 platform bringing support for 12-channel memory, PCIe 5.0, and support for memory expansion with Compute Express Link (CXL).
While Genoa will benefit from up to 96 Zen 4 cores and will be released towards the end of the year in Q4, AMD also announced Bergamo, which will be available in the first half of 2023, with Genoa-X and Siena also being available sometime in 2023. AMD's Genoa-X will feature up to 96 Zen 4 cores based on TSMC's 5 nm manufacturing node, with up to 1 GB of L3 cache per socket. AMD Siena will be predominantly targeted as a lower-cost platform and will feature up to 64 Zen 4 cores, with an optimized performance per watt, making it more affordable for the Edge and Telco markets.
AMD Unveils 5th Gen EPYC (Turin)
Perhaps the most significant announcement on AMD's Server CPU Roadmap going into 2024 is the plan to bring its 5th generation of EPYC processors codenamed 'Turin' to market sometime before the end of 2024. As expected, AMD hasn't shed many details on the Turin family of processors, but we expect it to be named the EPYC 7005 platform to follow its current EPYC name scheme.
We know that the Zen 5 cores will be based on a 4 nm mode (likely TSMC but not confirmed) and a 3 nm version, as highlighted in AMD's CPU Core Roadmap through to 2024. AMD also states there will be three variants of the Zen 5 core in its CPU roadmap, including Zen 5, Zen 5 with 3D V-Cache, and Zen 5c.
From the latest roadmap highlighting AMD's EPYC products, we know that AMD's 5th generation of EPYC processors is expected to launch sometime before the end of 2024.
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mode_13h - Friday, June 17, 2022 - link
Right, but that's because RAM slots are tied to CPUs. Once we move to CXL, that model is potentially broken and we might start to see a lot more 1-CPU configurations.Zoolook - Saturday, June 18, 2022 - link
There are still some usecases where 4 socket servers are used, when you need high transaction speed on one node on ever larger databases, like SAP Hana, granted the market share has plummeted thanks to the core explosion.schujj07 - Sunday, June 19, 2022 - link
So much of the need for quad sockets with SAP HANA is RAM slots. Many times it is cheaper to go 4 sockets with non L CPU and smaller DIMMs than dual socket with L CPU and larger DIMMs.CXL RAM sounds interesting but it will take a long time to come down in price. On top of that thing I've heard about is something like a RAM pool in a rack. How is that going to be setup to work with redundancy? Is it going to be like a SAN and have dual controllers? Right now if a host goes down you only have the VMs on that host crash. If your CXL RAM pool crashes you could have an entire racks worth of VMs crash. Then you might not be able to restart them all in you only have a single rack as you won't have enough RAM.
mode_13h - Monday, June 20, 2022 - link
> I've heard about is something like a RAM pool in a rack.> How is that going to be setup to work with redundancy?
PCIe would already seem to lay the foundations for what you'd need, with features like bifurcation. So, you could split the rack into two, redundant pools with each node having a link to each.
The only thing that's complicated by that scenario is cache coherence, but maybe CXL solves that at the protocol level.
david@van.dromme.net - Thursday, June 30, 2022 - link
Once over a certain number of cores you will find there is diminishing interest for multiple sockets, but yes - the number of memory sockets and the price for larger DIMMs surely plays a role as well as the licensing models of OS or virtualization vendors like Vmware or Microsoft. >=4 socket are niche market (mostly HPC, large databases, SAP, etc...). Overall dual socket is still the main server market, but it's been steadily loosing marketshare since the core counts are increasing per socket.ballsystemlord - Friday, June 10, 2022 - link
Ah, yes, don't type things late at night when overtired.I got that wrong.
hm4013824 - Monday, July 4, 2022 - link
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