Intel’s Manufacturing Roadmap from 2019 to 2029: Back Porting, 7nm, 5nm, 3nm, 2nm, and 1.4 nmby Dr. Ian Cutress on December 11, 2019 3:00 PM EST
Update: After some emailing back and forth, we can confirm that the slide that Intel's partner ASML presented at the IEDM conference is actually an altered version of what Intel presented for the September 2019 source. ASML added animations to the slide such that the bottom row of dates correspond to specific nodes, however at the time we didn't spot these animations (neither did it seem did the rest of the press). It should be noted that the correlation that ASML made to exact node names isn't so much a stretch of the imagination to piece together, however it has been requested that we also add the original Intel slide to provide context to what Intel is saying compared to what was presented by ASML. Some of the wording in the article has changed to reflect this. Our analysis is still relevant.
One of the interesting disclosures here at the IEEE International Electron Devices Meeting (IEDM) has been around new and upcoming process node technologies. Almost every session so far this week has covered 7nm, 5nm, and 3nm processes (as the industry calls them). What we didn’t expect to see disclosed was an extended roadmap of Intel’s upcoming manufacturing processes. It should be noted that the slide presented at the conference by Intel's partner, ASML, was modified slightly from its original source.
They say a slide is worth 1000 words. Here’s 1000 words on Intel's future.
Intel's slide, as presented in September
This is Intel's original slide, not detailing which nodes in which years. However, it should be easy enough to figure out that each one of the elements in the bottom row is the next process node along, otherwise the +/++ wouldn't make sense.
ASML applied these assumptions to the slide it presented at the IEDM keynote, but the company did not disclose that they had modified the slide.
Intel's slide with ASML's animations overlayed, as shown in the slide deck distributed by ASML
So let’s go through some key areas.
1.4nm in 2029
Intel expects to be on 2 year cadence with its manufacturing process node technology, starting with 10nm in 2019 and moving to 7nm EUV in 2021, then a fundamental new node in each of 2023, 2025, 2027, 2029. This final node is what ASML has dubbed '1.4nm'. This is the first mention on 1.4nm in the context of Intel on any Intel-related slide. For context, if that 1.4nm is indicative of any actual feature, would be the equivalent of 12 silicon atoms across.
It is perhaps worth noting that some of the talks at this year’s IEDM features dimensions on the order of 0.3nm with what are called ‘2D self-assembly’ materials, so something this low isn’t unheard of, but it is unheard of in silicon. Obviously there are many issues going that small that Intel (and its partners) will have to overcome.
+, ++, and Back Porting
In between each process node, as Intel has stated before, there will be iterative + and ++ versions of each in order to extract performance from each process node. The only exception to this is 10nm, which is already on 10+, so we will see 10++ and 10+++ in 2020 and 2021 respectively. Intel believes they can do this on a yearly cadence, but also have overlapping teams to ensure that one full process node can overlap with another.
The interesting element to these slides is the mention of back porting. This is the ability for a chip to be designed with one process node in mind, but perhaps due to delays, can be remade on an older ‘++’ version of a process node in the same timeframe. Despite Intel stating that they are disaggregating chip design from process node technology, at some point there has to be a commitment to a process node in order to start the layouts in silicon. At that point the process node procedure is kind of locked, especially when it goes to mask creation.
In the slide, it shows that Intel is going to allow a workflow such that any first gen 7nm design could be back ported to 10+++, any first gen 5nm design could be back ported to 7++, and so on. One can argue that this roadmap might not be so strict with the dates – we have seen Intel’s 10nm take a long time to bake, so expecting the company to move with a yearly cadence on + updates alongside a two-year cadence with main process technology nodes would appear to be a very optimistic and aggressive cadence strategy.
Note that this isn’t the first mention of back porting hardware designs when it comes to Intel. With the current delays to Intel’s 10nm process technology, it has been widely rumoured that some of Intel’s future CPU microarchitecture designs, originally designed with 10nm (or 10+, 10++) in mind might actually find a home on a 14nm process due to the success of that process node.
Development and Research
Normally with process node developments, there will be different teams working on each process node. This slide states that Intel is currently in development of its 10+++ optimizations as well as the 7nm family. The idea is that the ‘+’ updates are capturing the low hanging fruit from a design standpoint every generation, and the number represents a full node benefit. Interestingly we see Intel’s 7nm being based on 10++, whereas in the future Intel sees 5nm come from the base 7nm design, and 3nm coming from 5nm. There is no doubt that some of the optimizations that enter each +/++ update will filter into future designs as and when they are needed.
In this slide, we have Intel’s 2023 node currently in the definition stage. At this IEDM conference there’s a lot of talk about 5nm in this timeframe, so some of those improvements (such as manufacturing, materials, consistency, etc.) will ultimately end up in Intel’s process depending on which design houses they partner with (historically Applied Materials). It is worth noting that 5nm is listed as a 2023 node, which is around the time that ASML will start selling its ‘High NA’ EUV machines to help with better path definition during the manufacturing process. I’m not sure if High NA will intercept at 5nm or 3nm, assuming this Intel roadmap has its dates correct and Intel is able to stick to it, but it is something to consider
Beyond 2023, Intel is currently in the ‘path-finding’ and 'research' mode. As always when looking this far out, Intel is considering new materials, new transistor designs, and such. At this IEDM conference we’re seeing a lot of talk of gate-all-around transistors, either as nano-sheets or nano-wires, so no doubt we’re going to see some of that as FinFET runs out of steam. TSMC is still using FinFETs for its 5nm process (Intel’s 7nm equivalent), so I wouldn’t be surprised if we see something like nano-sheets then nano-wires (or even hybrid designs) come into Intel’s manufacturing stack.
It’s worth also pointing out, based on the title of this slide, that Intel still believes in Moore’s Law. Just don’t ask how much it’ll cost.
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CiccioB - Friday, December 13, 2019 - linkHuh?
Don't you know Intel is already developing its 7nm PP right now?
Or do you think they are going to wait for their 10nm problems to end before starting the development of the new PP?
Just by curiosity, do you know how long it takes to develop a new PP?
Korguz - Friday, December 13, 2019 - linkdont you know how to post a source for your claims ? ie a link or mention of a website.
its safe to assume that. but if all the companies that are able to make ICs get the equipment and tools to make them from the same handfull of companies, then for the most part.. the base design would be the same. if they would smart.. intel would be.. cause it could take them 3+ years before its ready.. and that being said.. this roadmap.. is bogus and garbage.. untill intel actually releases products for the given node. do you know how long it takes ???
look.. post links to your claims.. or your claims.. or just that ... yours.. nothing more
Zizy - Tuesday, December 10, 2019 - linkWell, considering 10nm issues I don't trust this plan at all. This backporting sounds ... troubling. Intel surely wishes they didn't have all those 10 nm problems or that at least that their CPUs could be remade to 14 nm process. But at the same time, backporting being an official strategy from now on means Intel doesn't trust their ability to offer great performance, yields or even basic ability to manufacture chips on their upcoming processes.
frenchy_2001 - Tuesday, December 10, 2019 - linkBackporting is the (very late) reply by intel to their current manufacturing problems.
Any other company would hve back ported their new architecture to their current node once they realized their manufacturing problems.
Not intel. They have been selling Skylake derivatives for 4+ years on 14nm process iterations.
Their new architecture was entirely married with their process node and they have been waiting all this time for manufacturing to catch up.
This backporting shows they are changing the way they design and implement new architecture to *NOT* fall back in that trap. Whether they will succeed is another matter...
Very aggressive road map. We'll see soon if 10nm was a single hiccup or a symptom of deeper problems. (by seeing when and how 7nm releases...)
TristanSDX - Tuesday, December 10, 2019 - link10 nm is not single hiccup. They had serious problems with 14nm.
Spunjji - Wednesday, December 11, 2019 - linkPeople have already forgotten what a mess the Broadwell "launch" was.
Nagorak - Wednesday, December 11, 2019 - linkTo be fair, AMD was so far behind until recently there was no reason not to just keep refreshing. Even now, Skylake is still faster for high end gaming due to the clockspeed advantage. AMD is the better buy across most of the product stack, but Intel still has that.
Spunjji - Wednesday, December 11, 2019 - linkIntel's not the better buy for high-end gaming - it's the better buy for *high refresh-rate 1080p gaming*. Anybody using VR / ultra-wide / 4K displays with high detail levels in recent games, which is what now constitutes high-end, is still going to be GPU limited.
NirXY - Wednesday, December 11, 2019 - linkJust because GPU's are limiting us today, doesn't mean they will still be as much next gen.
anonomouse - Tuesday, December 10, 2019 - linkConsidering this is a conference on device(transistor) technology and a slide deck presented by a device(transistor) research and manufacturing partner, does backport here really mean what people here are hoping it means?
i.e. are they potentially talking about back porting transistor/wire layouts and optimizations (metal stacks, Via materials, etc) to slightly older process nodes