Development of new fabrication technologies never stops at leading-edge companies such as TSMC. Therefore, it is not surprising to hear the annoucement that development of TSMC’s 3nm node is well underway, something the company publicly confirmed last week. As it appears, the manufacturing technology is out of its pathfinding mode and TSMC has already started engaging with early customers.

“On N3, the technology development progress is going well, and we are already engaging with the early customers on the technology definition,” said C.C. Wei, CEO and co-chairman of TSMC, in a conference call with investors and financial analysts. “We expect our 3-nanometer technology to further extend our leadership position well into the future.”

Since its N3 technology is in its early stages of development, TSMC doesn't currently talk about the specific characteristics of the process nor its advantages over N5. TSMC said that it had evaluated all possible transistor structure options for 3nm and came out with ‘a very good solution’ for its clients. The specification is under development and the company is confident it would meet requirements of its leading partnering customer.

One of TSMC’s arch-rivals, Samsung Foundry, plans to use nanosheet-based Gate-All-Around MBCFET transistors for its own 3nm (3GAAE) process technology. Since TSMC will have to be competitive with its rival, we expect the company to also advance its 3nm node significantly in comparison to its 5nm node. In fact, TSMC confirms that N3 is a brand-new process technology, not an improvement or iteration of N5.

Meanwhile, it is safe to say that that TSMC’s 3 nm node will use both deep ultraviolet (DUV) and extreme ultraviolet (EUV) lithography equipment. Since TSMC’s N5 uses up to 14 EUV layers, it is likely that N3 will go even higher in the amount of layers employed. The world’s largest contract maker of semiconductors also seems to be quite happy with its EUV progress and considers the technology important for its future.

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Source: TSMC

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  • 29a - Wednesday, July 24, 2019 - link

    Nano is not where the metric system ends.
  • FreckledTrout - Tuesday, July 23, 2019 - link

    It's already crazy enough that they are blasting tin droplets with high powered lasers to create EUV light. Now nanosheets. Almost certain this will be a Gate-All-Around approach maybee GAAFET? I'm kind of excited about what we can make using propper 3nm via GAAFET or MBCFET the densities will be insane.
  • stephenho - Tuesday, July 23, 2019 - link

    That might be the times, when 3nm begin to manufacture, that I will have to sell all semiconductor stocks, this is insanely risky. Whoever uses first can got burnt~!
  • FreckledTrout - Thursday, July 25, 2019 - link

    The risk is already there look at Intel's 10nm.
  • III-V - Wednesday, July 24, 2019 - link

    They're and blasting those droplets 10s of thousands of times per second. It's ridiculous
  • III-V - Wednesday, July 24, 2019 - link

    Launching and blasting *
  • Diogene7 - Thursday, July 25, 2019 - link

    According to the info on Wikichip website, the Apple A12 chip in 7nm that measure ~84mm2 has nearly ~7 billion transitors.

    That is a density > 80million transitors per mm2.

    It is said that TSMC 5nm has a transitor density 1.8x compared to 7nm, which would mean that, in theory, it would be possible to make chip in 5nm with > 140 million transitors per mm2.

    I would think that we may expect chip in 3nm to have ~ 200 million transistors or more per mm2.

    It seems that an Intel Pentium 4 at the beginning from 2000 had roughly 50 million transistors. So in theory you could fit the processing power of 4 pentium 4 processor (from year 2000) in 1mm2 using TSMC 3nm node....

    I would also think that we are getting closer to see the first chip with > 100 billion transistor in 2D...

    The years between 2020 and 2025 looks very exciting in terms of reaching some significant milestones...
  • Vitor - Tuesday, July 23, 2019 - link

    Those next 5 years won't be very comfortable for Intel. The ultra dominance is over.
  • Sychonut - Tuesday, July 23, 2019 - link

    Cool. Looking forward to Intel's 14+++++.
  • nunya112 - Wednesday, July 24, 2019 - link

    I think Intel will have to pay TSMC to use its IP and manufacturing Copyright in order to advance and to learn how to get past 14nm+

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