Development of new fabrication technologies never stops at leading-edge companies such as TSMC. Therefore, it is not surprising to hear the annoucement that development of TSMC’s 3nm node is well underway, something the company publicly confirmed last week. As it appears, the manufacturing technology is out of its pathfinding mode and TSMC has already started engaging with early customers.

“On N3, the technology development progress is going well, and we are already engaging with the early customers on the technology definition,” said C.C. Wei, CEO and co-chairman of TSMC, in a conference call with investors and financial analysts. “We expect our 3-nanometer technology to further extend our leadership position well into the future.”

Since its N3 technology is in its early stages of development, TSMC doesn't currently talk about the specific characteristics of the process nor its advantages over N5. TSMC said that it had evaluated all possible transistor structure options for 3nm and came out with ‘a very good solution’ for its clients. The specification is under development and the company is confident it would meet requirements of its leading partnering customer.

One of TSMC’s arch-rivals, Samsung Foundry, plans to use nanosheet-based Gate-All-Around MBCFET transistors for its own 3nm (3GAAE) process technology. Since TSMC will have to be competitive with its rival, we expect the company to also advance its 3nm node significantly in comparison to its 5nm node. In fact, TSMC confirms that N3 is a brand-new process technology, not an improvement or iteration of N5.

Meanwhile, it is safe to say that that TSMC’s 3 nm node will use both deep ultraviolet (DUV) and extreme ultraviolet (EUV) lithography equipment. Since TSMC’s N5 uses up to 14 EUV layers, it is likely that N3 will go even higher in the amount of layers employed. The world’s largest contract maker of semiconductors also seems to be quite happy with its EUV progress and considers the technology important for its future.

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Source: TSMC

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  • chrysrobyn - Wednesday, July 24, 2019 - link

    For non-Intel, that number has largely followed the width of the fin. Except for GF's "12" node, which is just a 14 with enhancements.
  • peevee - Wednesday, July 24, 2019 - link

    In connected news, Intel reports new successes in their Divercity and Inclusion program.
  • Thunder 57 - Wednesday, July 24, 2019 - link

    Maybe if instead they cared about hiring the best person for the job 10nm would be out already. Is it really so hard to believe that men and women are attracted to different professions?
  • peevee - Thursday, July 25, 2019 - link

    Deranged and ignorant SJWs and incompetent MBAs who hire them ruin everything, even the icon of American high tech. The company should fire everybody who is not an engineer or real scientist (physicist or chemist) by training and profession and get back to business.

    I am afraid it is too late now...
  • jospoortvliet - Friday, July 26, 2019 - link

    It must take a pathetic amount of frustration to ignore the simple and well researched fact that diverse teams outperform non-diverse counterparts, especially in tasks which require creative thinking like in high tech R&D as done at intel. But I take from your rather sad comment that you wouldn’t be able to function at such a level. I hope you at least managed to finish high school?!?
  • Jumangi - Saturday, July 27, 2019 - link

    Teams with the most talented and capable people regardless of their race or gender perform the best. You clearly have never worked in the industry before.
  • nivedita - Saturday, July 27, 2019 - link

    You, on the other hand, have clearly never worked anywhere before.
  • 69369369 - Sunday, July 28, 2019 - link


  • ianmills - Monday, July 29, 2019 - link

    Interesting that this is the path the Chinese government is taking. As long as you move to China you will be ok
  • rahvin - Tuesday, July 23, 2019 - link

    You should keep in mind while being amazed, which is totally justified, at this that like a previous poster mentioned, actual widths and marketing widths decoupled a few years ago.

    Transistors are essentially frozen at 16 to 22nm due to the quantum effects that take precedent at smaller gate widths (which is where finFET and other techs come in by raising in 3d a wider transistor out of a trace), while the traces get smaller they aren't close to the 3nm claimed. IIRC the traces on the current 7nm tech are about 100 silicon atoms wide and each node is about a ~10-20% reduction so this "3nm" is probably around 60-80 atoms wide traces.

    Still amazing, but just keep in mind marketing took over this term a few years ago and it became completely unreliable.

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