This year’s Galaxy S10 has been in a bit of an odd situation: Although Samsung continued to dual-source its SoCs, using both its own Exynos 9820 SoC as well as Qualcomm’s Snapdragon 855, the phone found itself in the unusual situation of pitting 8nm silicon against 7nm silicon from TSMC. So although the new Exynos 9820 did fairly well in testing and improved a lot over the Exynos 9810, the chip seemingly still had disadvantages against the competition when it came to power efficiency, likely linked to its process technology disadvantages. On top of the power efficiency disadvantages, the chip also had a notable die area disadvantage versus the Snapdragon, coming in at 127mm² versus the smaller 73mm² competition.

Samsung’s 7nm EUV process node was noted as having started production back in October of last year, although we’re not sure exactly which chip this was referring to, and we had hopes that it would be the chip for the S10 but alas it was not to be.

This time around, Samsung is seemingly bridging the gap with the introduction of the new Exynos 9825 – a 7nm LPP refresh of the Exynos 9820.

Samsung Exynos SoCs Specifications
SoC

Exynos 9820

Exynos 9825

CPU 2x M4 @ 2.73 GHz
2x 512KB pL2

2x Cortex A75 @ 2.31 GHz
2x 256KB pL2

4x Cortex A55 @ 1.95 GHz
No pL2's

Shared complex sL3 @ 4MB


2x M4 @ 2.73 GHz

2x Cortex A75 @ 2.4 GHz

4x Cortex A55 @ 1.95 GHz
GPU Mali G76MP12 @ 702 MHz Mali G76MP12 @ ? MHz
Memory
Controller
4x 16-bit CH
LPDDR4X @ 2093MHz
4x 16-bit CH
LPDDR4X @ 2093MHz
ISP Rear: 22MP
Front: 22MP
Dual: 16MP+16MP
Rear: 22MP
Front: 22MP
Dual: 16MP+16MP
Media 8K30 & 4K150 encode & decode
H.265/HEVC, H.264, VP9
8K30 & 4K150 encode & decode
H.265/HEVC, H.264, VP9
Integrated Modem Shannon 5000 Integrated LTE
(Category 20/13)

DL = 2000 Mbps
8x20MHz CA, 256-QAM

UL = 316 Mbps
3x20MHz CA, 256-QAM
Shannon 5000 Integrated LTE
(Category 20/13)

DL = 2000 Mbps
8x20MHz CA, 256-QAM

UL = 316 Mbps
3x20MHz CA, 256-QAM
Mfc. Process Samsung
8nm LPP
Samsung
7nm LPP (EUV)

The new chip very much looks like a die-shrink/mid-cycle refresh with largely the same IP generation as the 9820, still featuring Samsung’s M4 Cheetah cores as well as a Mali-G76 GPU. Samsung also doesn’t seem to have changed the clock frequencies of the chip very much: The M4 cores are still running at a peak frequency of 2.73GHz and the A55 cores also run at 1.95GHz. We do see a bump in the frequencies of the middle cores that goes up from 2.31GHz to 2.4GHz.

On the GPU side, Samsung has also stuck with the same GPU configuration as with 9820, using a MP12 configuration of the G76. According to the company the 9825's GPU is clocked higher - so it will outperform its predecessor - however the company has yet to disclose specific clockspeeds.

As for the integrated modem, Samsung has retained their Shannon 5000, a Category 20/13 modem. This modem has a peak download rate of 2 Gbps (with 8x carrier aggregration), while uploads top out at 316 Mbps. We had been wondering if Samsung would be able to squeeze in a 5G modem for this SoC, but it looks like it's just a bit too early for that. Instead, 5G can be accomplished by pairing the SoC with Samsung's 5G Exynos Modem 5100.

The new chip is likely to be featured in the new Galaxy Note10 – Samsung will continue to use Snapdragon chips for some markets, and this could be an explanation for the new chip not having that big improvements on the part of the CPU complex as it’s aiming for performance parity with the Snapdragon. We also have to note that Samsung would have to invest the process improvements into improving power efficiency rather than raising performance.

The chip reminds us of the Exynos 5430 from a few years ago which was also a process-shrink to the chip that ended up in the Galaxy S5, representing Samsung’s first 20nm silicon. That chip never ended up in the popular flagship products, but seemingly did serve a purpose as a pipe-cleaner and learning platform for the new process node. The new Exynos 9825 could end up in a similar situation, although being used in the Note10, it won’t nearly have an as long lifespan as we don’t expect it to power the Galaxy S11 next year.

Source: Samsung

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  • Santoval - Thursday, August 8, 2019 - link

    Ninja'd. According to Wikichip Samsung's UHD (Ultra High Density, intended for mobile & low power SoCs) 8nm node variant has a density of ~61 MTr/mm² (MTr = million transistors).
    SemiWiki reports that Samsung's 7nm LPP EUV node will have a "minimum" transistor density of 95 MTr/mm², in other words a 55% higher transistor density.

    Assuming the design of Exynos 9825 is identical to that of 9820, and as it appears it is, and assuming the density will increase by 55% in the entire stack of the SoC (from FEOL to BEOL, not just in FEOL), which is not certain, let's estimate the die area decrease from the 55% increase in density. Let's rather make it a nice round 50% density increase to account for a potential density misalignment in the BEOL stack :

    A doubling of density leads (obviously) to a 50% smaller die area, so a 50% higher density should make the die ~25% smaller. 127 mm² - 25% is ~95 mm². That's still larger than the 73 mm² of the equivalent Snapdragon, but it's quite smaller than 127 mm², with plenty more usable dies per wafer.
    Reply
  • Anymoore - Wednesday, August 7, 2019 - link

    The EUV tools in use so far have insufficient uptime for manufacturing. So I wouldn't expect a steady volume at this point. Reply
  • name99 - Wednesday, August 7, 2019 - link

    How do you know?
    Seems to me Samsung's decision makers are likely more informed about their EUV uptimes and throughput than what J Random Internet user has managed to glean from year-old conference reports and random tweets.
    Reply
  • Anymoore - Wednesday, August 7, 2019 - link

    It is from this year's announcement of NXE:3400C by ASML. I don't think Samsung claims high throughput and uptime either. Reply
  • name99 - Wednesday, August 7, 2019 - link

    ASML said no such thing. They actually said "Production and service capability in place to enable
    ASML required volume in time"

    https://staticwww.asml.com/doclib/investor/financi...
    pg 16

    Of course it'a always nice to do things faster, and the C will be a more desirable machine than the B. But ASML said nothing close to what you claim.
    Reply
  • Anymoore - Wednesday, August 7, 2019 - link

    I got it here: https://semiwiki.com/semiconductor-services/ic-kno...

    So it's not yet at the target, and the C introduction makes it look like large changes are necessary.
    Reply
  • Santoval - Friday, August 9, 2019 - link

    Samsung's "decision makers" have a vested interest to overpromise their company's prowess, so they are not exactly the most reliable sources. And when you overpromise you underdeliver. Hell, Intel have been doing this since 2015 with their 10nm node, year after year and quarter after quarter, and they still have not released any 10nm fabbed products in the market (that December 2017 limited launch of that half broken dual core Cannon Lake i3, exclusively for some Chinese schools, was not a release, it was a "let's pull the wool over the eyes of our most gullible investors by reporting a nominal 2017 release of a 10nm fabbed CPU" tactic).

    By now you should be suspicious enough to not trust anything EUV related various companies with a vested interest in/from EUV announce, since EUV has been delayed even longer than Intel's 10nm node (that's surely quite a feat!). The EUV situation is still so sketchy companies will insert it only for some non critical layers (apparently the lowest metal layers of the BEOL stack, probably the M0 to M3 layers) at first.

    Evidently the pellicles for the EUV photomasks are not yet as good as the fabs would like them to be, and without pellicles you cannot print anything in the FEOL stack, but you can etch a few layers of the BEOL stack with "bare" masks, at a slight risk of damaging or soiling them. They hope the pellicle issue and some other less serious issues will have been resolved by the time the 5nm node starts HVM though.
    Reply
  • Arsenica - Wednesday, August 7, 2019 - link

    EUV tools may not be able to replace the volume of 193i tools right now, but as this is just a tweaked version of Samsung's 8nm process they are not using EUV for all high resolution steps.

    We can be pretty sure that they are still using 193i multiple patterning for the fins and the use of EUV is likely limited to contact holes and/or Metal1 (steps in which using EUV is likely to result in increased yields with current technology). So Samsung will likely be able to provide a volume similar to that of their 8nm process.

    EUV tools won't replace 193i tools for FEOL steps before the 5nm-class nodes or maybe until they abandon FinFETs for Gate-all-around FETs
    Reply
  • Anymoore - Wednesday, August 7, 2019 - link

    Samsung's multipatterning lithography for BEOL is simply inferior compared to their competitor(s); which is why they have so many mask steps. Reply
  • Zingam - Wednesday, August 7, 2019 - link

    AV1 support? Reply

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