Intel Lists New Atom Core: Tremont to Come After Goldmont Plus
by Anton Shilov on April 23, 2018 5:00 PM EST
Intel has recently updated its developer documentation for instruction set extensions, and in the process has disclosed information on both new instructions for and the codename of its next-generation low-power processor microarchitecture. Dubbed "Tremont", the forthcoming processor core look to replace Goldmont Plus in the upcoming Atom, Celeron, and Pentium Silver-branded SoCs.
According to the Intel Architecture Instruction Set Extensions (ISE) and Future Features Programming Reference document, the Goldmont Plus microarchitecture will not be the end of the road for Intel’s low-cost/low-power cores. In the coming years it will be succeeded by the codenamed Tremont microarchitecture and its successors. On the manufacturing side of matters, nothing has officially been disclosed, but right now our suspicion is that processors based on the Tremont will be made using the company’s 10 nm process technology. To date we haven't seen Intel use their enhanced “+” and “++” 14nm process technologies to make SoCs for entry-level and energy-efficient PCs - as the original 14nm provides better density - so it seems unlikely that Intel would start now.
A key question about the Tremont is what architecturaly improvements it will bring. While Intel's document does specify the new instructions, it doesn't offer any general architectural insight. Intel's general trend thus far since Silvermont has been to gradually widen their out-of-order execution design, starting with two-way, moving to three-way (Goldmont), and then to a three-way front-end plus a four-way allocation and retirement backend. So it may be that we see Intel go this route, as they already have a number of tricks left in their bag from Core, and it meshes well with the high density aspects of their 10nm processes, which favors more complex processors.
As for the ISE improvements, Intel’s Tremont will feature CLWB, GFNI (SSE-based), ENCLV, and Split Lock Detection instruction set extensions, which are also set to arrive with Intel’s Ice Lake processors. Also set to arrive with Tremont will be CLDEMOTE, direct store, and user wait instructions (see details in the table below). Unlike the earlier instructions, these are unique to Tremont and are not scheduled to be supported by the Ice Lake (or other documented Intel’s cores).
| New Instruction Set Extensions of Goldmont Plus and Tremont CPUs | |||||
| Instruction | Purpose | Description | |||
| Goldmont Plus | PTWRITE Write Data to a Processor Trace Packet |
Debugging | Unclear. | ||
| UMIP User-Mode Instruction Prevention |
Security | Prevents execution of certain instructions if the Current Privilege Level (CPL) is greater than 0. If these instructions were executed while in CPL > 0, user space applications could have access to system-wide settings such as the global and local descriptor tables, the task register and the interrupt descriptor table. | |||
| RDPID Read Processor ID |
General | Quickly reads processor ID to discover its feature set and apply optimizations/use specific code path if possible. | |||
| Tremont | CLWB Cache Line Write Back |
Performance | Writes back modified data of a cache line similar to CLFLUSHOPT, but avoids invalidating the line from the cache (and instead transitions the line to non-modified state). CLWB attempts to minimize the compulsory cache miss if the same data is accessed temporally after the line is flushed if the same data is accessed temporally after the line is flushed. | ||
| GFNI (SSE) | Security | SSE-based acceleration of Galois Field Affine Transformation alghorithms. | |||
| ENCLV | Security | Further enhancement of SGX version 1 capabilities. | |||
| CLDEMOTE | Performance | Enables CPU to demote a cache line with a specific adress from the nearest cache to a more distant cache without writing back to memory. Speeds up access to this line by other cores within a CPU. | |||
| Direct stores: MOVDIRI, MOVDIR64B | Performance | ||||
| User wait: TPAUSE, UMONITOR, UMWAIT | Power | Direct CPU to enter certain stages before an event happens. | |||
| Split Lock Detection | |||||
| Source: Intel Architecture Instruction Set Extensions and Future Features Programming Reference (pages 12 and 13) | |||||
The fact that Intel is readying its “Future Tremont and later” microarchitectures reveals that even after the company withdrew from smartphone SoCs, it sees plenty of applications that could use its low-power/low-cost Atom cores. There is sitll a notable market for budget PCs as well as embedded and semi-embeded markets for items like IoT edge devices, all of which Intel intends to continue serving with the line of smaller, cheaper cores. Meanwhile, consistent ILP and performance improvements as well as introduction of new ISEs to these microarchitectures show that Intel wants these cores to offer competitive performance to other low-cost processors, while still maintaining near feature set parity to Intel's high-performance cores.
Related Reading
- Intel Launches New Pentium Silver and Celeron Atom Processors: Gemini Lake is Here
- Intel Documents Point to AVX-512 Support for Cannon Lake Consumer CPUs
- Intel Quietly Launches Apollo Lake SoC: Goldmont CPU, 6 SKUs, 6 & 10 Watts
- Intel's Changing Future: Smartphone SoCs Broxton & SoFIA Officially Cancelled
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GreenReaper - Thursday, October 24, 2019 - link
Good question. Ars Technica asked about the security and related performance implications and received essentially no reply beyond "it's secure": "I pressed Intel Senior Principal Engineer Stephen Robinson pretty hard on the security aspects of this point—specifically, does Core-class branch prediction mean Core-class speculative execution vulnerabilities to exploits such as Spectre and Meltdown?Robinson refused to speak with any detail on either Tremont's vulnerability to speculative execution attacks, or whether it would require software mitigations such as those necessary in Core class processors. He did not seem prepared for or comfortable with this line of questioning. Robinson also refused to comment on the performance implications of software mitigations if required..."
https://arstechnica.com/gadgets/2019/10/intel-want...
Kevin G - Tuesday, April 24, 2018 - link
One oddity in that document is that Cannon Lake is going to be picking up AVX-512. This is note worthy as the only Cannon Lake chips are going to be for mobile as Intel has gutted most of the Cannon Lake line up (desktop Cannon Lake has been dead for awhile). Putting a big fat power hungry SIMD unit into mobile parts seems weird when desktops don't yet have those ISA extensions.CaedenV - Tuesday, April 24, 2018 - link
... Atom is still a thing? Didnt they announce they were killing it a few years ago? Didn't the recent Cisco recall atom bug put a death nail in the platform?Don't get me wrong, I have always been a fan of Atom chips. Cheap small (all be it slow) x86 chips are a good thing in my book. But with the problems and lack of traction I thought Intel would have moved on to something else by now.
mode_13h - Tuesday, April 24, 2018 - link
No, they killed off their cell phone SoC products, which were built around the Atom-series cores.They still sell Atom-based products into entry-level laptops, embedded applications, low-power servers, and HPC (Xeon Phi).
https://ark.intel.com/products/codename/80644/Apol...
https://ark.intel.com/products/codename/83915/Gemi...
https://ark.intel.com/products/series/97941/Intel-...
https://ark.intel.com/products/series/87465/Intel-...
https://ark.intel.com/products/series/132784/Intel...
They also bought Altera (FPGAs) and several machine learning / computer vision chips that all feature hardwired (mostly ARMs and SPARC). Intel probably intends to replace some of those with Atom-family cores.
CityBlue - Wednesday, April 25, 2018 - link
> They still sell Atom-based products into entry-level laptops,"sell"? Now that's a bit of a stretch, as I'm pretty sure Intel were giving them away at $0 cost (or even less) in order to entice Shenzen manufacturers into using something other than ARM - it was always difficult to understand how the entire, finished tablet could retail at a price lower than the known Intel tray price of the CPU it contained. It's why the Intel mobile business lost $billions every year, as they actually "sold" squat, and just another example of Intel's extremely dodgy business practices.
mode_13h - Thursday, April 26, 2018 - link
You're conflating the entry-level laptop (AKA ChromeBook) market with their tablet SoCs.Who can say why Apollo Lake and Gemini Lake are so prevalent in that market, today? I agree they're certainly not selling those chips at the listed tray price, but that doesn't necessarily mean they're taking a loss on them.