Samsung’s 8LPP Process Technology Qualified, Ready for Production
by Anton Shilov on October 19, 2017 11:00 AM EST
Samsung this week announced that its 8LPP fabrication process, which it formally introduced earlier this year, had passed qualification tests. The manufacturing technology will be used to produce advanced SoCs next year and will be Samsung’s final leading edge process based solely on DUV lithography before the company adopts EUV for select layers with its 7LPP process node.
The 8LPP fabrication technology is an evolution of Samsung’s 10 nm node that uses narrower metal pitches and promises a 10% area reduction (at the same complexity) as well as a 10% lower power consumption (at the same frequency and complexity) compared to the 10LPP process. Samsung does not disclose which standard cell libraries are used by the 8LPP, but the 10LPP relies on 8.75T and 10.5T, so it is logical to expect the 8LPP to use similar ones. Samsung does not disclose whether the 8LPP relies on quadruple patterning techniques, or if it continues to use triple patterning like the company’s 10LPE/10LPP processes, but QPT is an option to shrink die sizes at the increase in cost (and potential defects).
| Advertised PPA Improvements of New Process Technologies Data announced by companies during conference calls, press briefings and in press releases |
||||||||
| 14LPP vs 28LPP |
10LPE vs 14LPE |
10LPE vs 14LPP |
10LPP vs 10LPE |
10LPU vs 10LPE |
8LPP vs 10LPP |
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| Power | 60% | 40% | 30% | ~15% | ? | 10% | ||
| Performance | 40% | 27% | >10% | ~10% | ? | ? | ||
| Area Reduction | 50% | 30% | 30% | none | ? | 10% | ||
Samsung plans to use the 8LPP manufacturing technology to produce SoCs for various applications, including smartphones, cryptocurrency and networks/servers, but does not elaborate on exact designs or clients. The only thing we do know is that Qualcomm will be one of the first customers to adopt the 8LPP and that the company expects the new technology to ramp up fast (which possibly means that it uses the same libraries and manufacturing equipment as the 10 nm nodes).
“8LPP will have a fast ramp since it uses proven 10 nm process technology while providing better performance and scalability than current 10nm-based products” said RK Chunduru, a senior vice president of Qualcomm.
Neither Samsung nor Qualcomm are disclosing when they expect to ship their first 8LPP chips, but since the technology has passed qualification tests (meaning that quality and reliability of ICs made using the technology meet certain guidelines, such as those proposed by JEDEC), we would expect the SoCs to arrive in the coming quarters.
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Source: Samsung
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Wilco1 - Thursday, October 19, 2017 - link
A "standard node" metric has been proposed, see last graph in https://www.semiwiki.com/forum/content/6895-standa...However as the article explains, there is no single metric that can fully describe each node so they can be compared. Even if transistors had identical dimensions between 2 processes, there would be major differences in libraries, design rules, metal layers, performance, power, yield, cost, volume etc etc.
name99 - Friday, October 20, 2017 - link
Did it ever occur to you that no such metric exists?One process may be superior for performance, another superior for power, another superior for cost, another superior for density?
You're asking something like "give me ONE number to show what's the best car".
HollyDOL - Thursday, October 19, 2017 - link
And they claim 'size doesn't matter' :ppeevee - Friday, October 20, 2017 - link
"The 8LPP fabrication technology is an evolution of Samsung’s 10 nm node that uses narrower metal pitches and promises a 10% area reduction"Samsung's shenanigans again. If area reduction is only 10%, then linear reduction is ~5%, so compared to 10nm it should be named 9.5nm process. :) Of course "10nm" is not 10nm to begin with. It is all still closer to 20nm as related to 45nm processes when things still used to be marked more or less honestly.